| 2007 |
|---|
| 6 | EE | Shibaji Banerjee,
Dipanwita Roy Chowdhury,
Bhargab B. Bhattacharya:
An Efficient Scan Tree Design for Compact Test Pattern Set.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1331-1339 (2007) |
| 2006 |
|---|
| 5 | EE | Shibaji Banerjee,
Dipanwita Roy Chowdhury:
Built-In Self-Test for Flash Memory Embedded in SoC.
DELTA 2006: 379-384 |
| 4 | EE | Shibaji Banerjee,
Dipanwita Roy Chowdhury,
Bhargab B. Bhattacharya:
An Efficient Scan Tree Design for Compact Test Pattern Set.
VLSI Design 2006: 175-180 |
| 3 | EE | Shibaji Banerjee,
Debdeep Mukhopadhyay,
C. V. G. Rao,
Dipanwita Roy Chowdhury:
An integrated DFT solution for mixed-signal SOCs.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1368-1377 (2006) |
| 2005 |
|---|
| 2 | EE | Debdeep Mukhopadhyay,
Shibaji Banerjee,
Dipanwita Roy Chowdhury,
Bhargab B. Bhattacharya:
CryptoScan: A Secured Scan Chain Architecture.
Asian Test Symposium 2005: 348-353 |
| 1 | EE | Shibaji Banerjee,
Debdeep Mukhopadhyay,
Dipanwita Roy Chowdhury:
Computer Aided Test (CAT) Tool for Mixed Signal SOCs.
VLSI Design 2005: 787-790 |
