| 2008 |
|---|
| 90 | EE | DiaaEldin Khalil,
Yehea I. Ismail:
A global interconnect link design for many-core microprocessors.
IFMT 2008: 14 |
| 89 | EE | Sami Kirolos,
Yehia Massoud,
Yehea I. Ismail:
Power-supply-variation-aware timing analysis of synchronous systems.
ISCAS 2008: 2418-2421 |
| 88 | EE | Sami Kirolos,
Yehia Massoud,
Yehea I. Ismail:
Accurate analytical delay modeling of CMOS clock buffers considering power supply variations.
ISCAS 2008: 3394-3397 |
| 87 | EE | Yehea I. Ismail:
Interconnect design and limitations in nanoscale technologies.
ISCAS 2008: 780-783 |
| 86 | EE | DiaaEldin Khalil,
Yehea I. Ismail,
Muhammad M. Khellah,
Tanay Karnik,
Vivek De:
Analytical Model for the Propagation Delay of Through Silicon Vias.
ISQED 2008: 553-556 |
| 85 | EE | D. E. Khalil,
Muhammad M. Khellah,
Nam-Sung Kim,
Yehea I. Ismail,
Tanay Karnik,
V. K. De:
Accurate Estimation of SRAM Dynamic Stability.
IEEE Trans. VLSI Syst. 16(12): 1639-1647 (2008) |
| 84 | EE | Ja Chun Ku,
Yehea I. Ismail:
Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 241-248 (2008) |
| 2007 |
|---|
| 83 | EE | Debasish Das,
Ahmed Shebaita,
Yehea I. Ismail,
Hai Zhou,
Kip Killpack:
NostraXtalk: a predictive framework for accurate static timing analysis in udsm vlsi circuits.
ACM Great Lakes Symposium on VLSI 2007: 25-30 |
| 82 | EE | Ahmed Shebaita,
Dusan Petranovic,
Yehea I. Ismail:
Including inductance in static timing analysis.
ICCAD 2007: 686-691 |
| 81 | EE | Frank Huebbers,
Ali Dasdan,
Yehea I. Ismail:
Multi-layer interconnect performance corners for variation-aware timing analysis.
ICCAD 2007: 713-718 |
| 80 | EE | Jieyi Long,
Ja Chun Ku,
Seda Ogrenci Memik,
Yehea I. Ismail:
A self-adjusting clock tree architecture to cope with temperature variations.
ICCAD 2007: 75-82 |
| 79 | EE | Ahmed Shebaita,
Yehea I. Ismail:
Variable Threshold Voltage Design Scheme for CMOS Tapered Buffers.
ISCAS 2007: 1385-1388 |
| 78 | EE | Ja Chun Ku,
Yehea I. Ismail:
Attaining Thermal Integrity in Nanometer Chips.
ISCAS 2007: 3223-3226 |
| 77 | EE | Ja Chun Ku,
Yehea I. Ismail:
A Compact and Accurate Temperature-Dependent Model for CMOS Circuit Delay.
ISCAS 2007: 3736-3739 |
| 76 | EE | DiaaEldin Khalil,
Yehea I. Ismail:
Approximate Frequency Response Models for RLC Power Grids.
ISCAS 2007: 3784-3787 |
| 75 | EE | Ja Chun Ku,
Yehea I. Ismail:
Thermal-aware methodology for repeater insertion in low-power VLSI circuits.
ISLPED 2007: 86-91 |
| 74 | EE | Ke Meng,
Frank Huebbers,
Russ Joseph,
Yehea I. Ismail:
Modeling and Characterizing Power Variability in Multicore Architectures.
ISPASS 2007: 146-157 |
| 73 | EE | Serkan Ozdemir,
Arindam Mallik,
Ja Chun Ku,
Gokhan Memik,
Yehea I. Ismail:
Variable latency caches for nanoscale processor.
SC 2007: 20 |
| 72 | EE | Ja Chun Ku,
Serkan Ozdemir,
Gokhan Memik,
Yehea I. Ismail:
Thermal Management of On-Chip Caches Through Power Density Minimization.
IEEE Trans. VLSI Syst. 15(5): 592-604 (2007) |
| 71 | EE | Ja Chun Ku,
Yehea I. Ismail:
Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits.
IEEE Trans. VLSI Syst. 15(8): 963-970 (2007) |
| 70 | EE | Ja Chun Ku,
Yehea I. Ismail:
On the Scaling of Temperature-Dependent Effects.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1882-1888 (2007) |
| 69 | EE | Shizhong Mei,
Yehea I. Ismail:
An Accurate Low-Iteration Algorithm for Effective Capacitance Computation.
Journal of Circuits, Systems, and Computers 16(5): 791-800 (2007) |
| 2006 |
|---|
| 68 | | Gang Qu,
Yehea I. Ismail,
Narayanan Vijaykrishnan,
Hai Zhou:
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006
ACM 2006 |
| 67 | EE | Ja Chun Ku,
Serkan Ozdemir,
Gokhan Memik,
Yehea I. Ismail:
Power density minimization for highly-associative caches in embedded processors.
ACM Great Lakes Symposium on VLSI 2006: 100-104 |
| 66 | EE | Ja Chun Ku,
Yehea I. Ismail:
Area optimization for leakage reduction and thermal stability in nanometer scale technologies.
ASP-DAC 2006: 231-236 |
| 65 | EE | Frank Huebbers,
Ali Dasdan,
Yehea I. Ismail:
Computation of accurate interconnect process parameter values for performance corners under process variations.
DAC 2006: 797-800 |
| 64 | EE | Ahmed Shebaita,
Dusan Petranovic,
Yehea I. Ismail:
Importance of volume discretization of single and coupled interconnects.
ICCAD 2006: 119-126 |
| 63 | EE | Debjit Sinha,
DiaaEldin Khalil,
Yehea I. Ismail,
Hai Zhou:
A timing dependent power estimation framework considering coupling.
ICCAD 2006: 401-407 |
| 62 | EE | Debasish Das,
Ahmed Shebaita,
Hai Zhou,
Yehea I. Ismail,
Kip Killpack:
FA-STAC: A Framework for Fast and Accurate Static Timing Analysis with Coupling.
ICCD 2006 |
| 61 | EE | DiaaEldin Khalil,
Yehea I. Ismail:
Optimum sizing of power grids for IR drop.
ISCAS 2006 |
| 60 | EE | Maged Ghoneima,
Yehea I. Ismail,
Muhammad M. Khellah,
Vivek De:
Reducing the data switching activity of serialized datastreams.
ISCAS 2006 |
| 59 | EE | Keith A. Bowman,
James Tschanz,
Muhammad M. Khellah,
Maged Ghoneima,
Yehea I. Ismail,
Vivek De:
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.
ISLPED 2006: 79-84 |
| 58 | EE | Maged Ghoneima,
Yehea I. Ismail,
Muhammad M. Khellah,
Vivek De:
Reducing the Data Switching Activity on Serial Link Buses.
ISQED 2006: 425-432 |
| 57 | EE | Masud H. Chowdhury,
Yehea I. Ismail:
Realistic scalability of noise in dynamic circuits.
IEEE Trans. VLSI Syst. 14(6): 637-641 (2006) |
| 56 | EE | Maged Ghoneima,
Yehea I. Ismail,
Muhammad M. Khellah,
James Tschanz,
Vivek De:
Formal derivation of optimal active shielding for low-power on-chip buses.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 821-836 (2006) |
| 2005 |
|---|
| 55 | | John Lach,
Gang Qu,
Yehea I. Ismail:
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005
ACM 2005 |
| 54 | EE | Noha Mahmoud,
Maged Ghoneima,
Yehea I. Ismail:
Physical limitations on the bit-rate of on-chip interconnects.
ACM Great Lakes Symposium on VLSI 2005: 13-19 |
| 53 | EE | Chirayu S. Amin,
Noel Menezes,
Kip Killpack,
Florentin Dartu,
Umakanta Choudhury,
Nagib Hakim,
Yehea I. Ismail:
Statistical static timing analysis: how simple can we get?
DAC 2005: 652-657 |
| 52 | EE | Chirayu S. Amin,
Yehea I. Ismail,
Florentin Dartu:
Piece-wise approximations of RLCK circuit responses using moment matching.
DAC 2005: 927-932 |
| 51 | EE | Gokhan Memik,
Masud H. Chowdhury,
Arindam Mallik,
Yehea I. Ismail:
Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files.
DSN 2005: 770-779 |
| 50 | | Maged Ghoneima,
Yehea I. Ismail,
Muhammad M. Khellah,
James Tschanz,
Vivek De:
Serial-link bus: a low-power on-chip bus architecture.
ICCAD 2005: 541-546 |
| 49 | | Ahmed M. Shebaita,
Chirayu S. Amin,
Florentin Dartu,
Yehea I. Ismail:
Expanding the frequency range of AWE via time shifting.
ICCAD 2005: 935-938 |
| 48 | EE | Muhammad M. Khellah,
Maged Ghoneima,
James Tschanz,
Yibin Ye,
Nasser Kurd,
Javed Barkatullah,
Srikanth Nimmagadda,
Yehea I. Ismail:
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.
ICCD 2005: 253-257 |
| 47 | EE | Yehea I. Ismail,
Muhammad M. Khellah,
Maged Ghoneima,
James Tschanz,
Yibin Ye,
Vivek De:
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.
ISCAS (1) 2005: 592-595 |
| 46 | EE | Maged Ghoneima,
Yehea I. Ismail:
Accurate decoupling of capacitively coupled buses.
ISCAS (4) 2005: 4146-4149 |
| 45 | EE | Ja Chun Ku,
Serkan Ozdemir,
Gokhan Memik,
Yehea I. Ismail:
Thermal Management of On-Chip Caches Through Power Density Minimization.
MICRO 2005: 283-293 |
| 44 | EE | Chirayu S. Amin,
Masud H. Chowdhury,
Yehea I. Ismail:
Realizable reduction of interconnect circuits including self and mutual inductances.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 271-277 (2005) |
| 43 | EE | Maged Ghoneima,
Yehea I. Ismail:
Optimum positioning of interleaved repeaters in bidirectional buses.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 461-469 (2005) |
| 42 | EE | Chirayu S. Amin,
Florentin Dartu,
Yehea I. Ismail:
Weibull-based analytical waveform model.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1156-1168 (2005) |
| 2004 |
|---|
| 41 | EE | Yehea I. Ismail,
Chirayu S. Amin:
Computation of signal threshold crossing times directly from higher order moments.
ICCAD 2004: 246-253 |
| 40 | EE | Chirayu S. Amin,
Florentin Dartu,
Yehea I. Ismail:
Modeling unbuffered latches for timing analysis.
ICCAD 2004: 254-260 |
| 39 | EE | Maged Ghoneima,
Yehea I. Ismail:
Formal derivation of optimal active shielding for low-power on-chip buses.
ICCAD 2004: 800-807 |
| 38 | | Maged Ghoneima,
Yehea I. Ismail:
Low power coupling-based encoding for on-chip buses.
ISCAS (2) 2004: 325-328 |
| 37 | | Maged Ghoneima,
Yehea I. Ismail:
Effect of relative delay on the dissipated energy in coupled interconnects.
ISCAS (2) 2004: 525-528 |
| 36 | EE | Daniel Dai,
Yehea I. Ismail,
Wei Wang,
Hanif M. Ladak:
Powder-based fabrication techniques for single-wall carbon nanotube circuits.
ISCAS (3) 2004: 701-704 |
| 35 | EE | Maged Ghoneima,
Yehea I. Ismail:
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.
ISLPED 2004: 66-69 |
| 34 | EE | Masud H. Chowdhury,
Yehea I. Ismail:
Possible Noise Failure Modes in Static and Dynamic Circuits.
IWSOC 2004: 123-126 |
| 33 | EE | Maged Ghoneima,
Yehea I. Ismail:
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses.
IEEE Trans. VLSI Syst. 12(12): 1348-1359 (2004) |
| 32 | | Shizhong Mei,
Yehea I. Ismail:
Modeling skin and proximity effects with reduced realizable RL circuits.
IEEE Trans. VLSI Syst. 12(4): 437-447 (2004) |
| 31 | EE | Yehea I. Ismail,
Chirayu S. Amin:
Computation of signal-threshold crossing times directly from higher order moments.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1264-1276 (2004) |
| 2003 |
|---|
| 30 | EE | Chirayu S. Amin,
Masud H. Chowdhury,
Yehea I. Ismail:
Realizable RLCK circuit crunching.
DAC 2003: 226-231 |
| 29 | EE | Shizhong Mei,
Chirayu S. Amin,
Yehea I. Ismail:
Efficient model order reduction including skin effect.
DAC 2003: 232-237 |
| 28 | EE | Maged Ghoneima,
Yehea I. Ismail:
Optimum positioning of interleaved repeaters In bidirectional buses.
DAC 2003: 586-591 |
| 27 | EE | Chirayu S. Amin,
Florentin Dartu,
Yehea I. Ismail:
Weibull Based Analytical Waveform Model.
ICCAD 2003: 161-168 |
| 26 | EE | Masud H. Chowdhury,
Chirayu S. Amin,
Yehea I. Ismail,
Chandramouli V. Kashyap,
Byron Krauter:
Realizable reduction of RLC circuits using node elimination.
ISCAS (3) 2003: 494-497 |
| 25 | EE | Shizhong Mei,
Yehea I. Ismail:
Modeling skin effect with reduced decoupled R-L circuits.
ISCAS (4) 2003: 588-591 |
| 24 | EE | Noha H. Mahmoud,
Yehea I. Ismail:
Accurate rise time and overshoots estimation in RLC interconnects.
ISCAS (5) 2003: 477-480 |
| 23 | EE | Masud H. Chowdhury,
Yehea I. Ismail:
Analysis of Coupling Noise in Dynamic Circuit.
IWSOC 2003: 320-325 |
| 22 | EE | Yehea I. Ismail:
Improved model-order reduction by using spacial information in moments.
IEEE Trans. VLSI Syst. 11(5): 900-908 (2003) |
| 21 | EE | Yehea I. Ismail,
Eby G. Friedman:
On the Extraction of On-Chip Inductance.
Journal of Circuits, Systems, and Computers 12(1): 31-40 (2003) |
| 2002 |
|---|
| 20 | EE | Yehea I. Ismail:
Efficient model order reduction via multi-node moment matching.
ICCAD 2002: 767-774 |
| 19 | EE | Masud H. Chowdhury,
Yehea I. Ismail,
Chandramouli V. Kashyap,
Byron Krauter:
Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance.
ISCAS (4) 2002: 197-200 |
| 18 | EE | Yehea I. Ismail:
Evaluating noise pulses in RC networks due to capacitive coupling.
ISCAS (5) 2002: 653-656 |
| 17 | EE | Yehea I. Ismail,
Byron Krauter:
Guest editorial: special issue on on-chip inductance in high-speed integrated circuits.
IEEE Trans. VLSI Syst. 10(6): 683-684 (2002) |
| 16 | EE | Yehea I. Ismail:
On-chip inductance cons and pros.
IEEE Trans. VLSI Syst. 10(6): 685-694 (2002) |
| 15 | EE | Yehea I. Ismail,
Eby G. Friedman:
DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 131-144 (2002) |
| 14 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Inductance Effects in RLC Trees.
Journal of Circuits, Systems, and Computers 11(3): 305- (2002) |
| 2001 |
|---|
| 13 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Exploiting the on-chip inductance in high-speed clock distribution networks.
IEEE Trans. VLSI Syst. 9(6): 963-973 (2001) |
| 2000 |
|---|
| 12 | EE | Yehea I. Ismail,
Eby G. Friedman:
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.
IEEE Trans. VLSI Syst. 8(2): 195-206 (2000) |
| 11 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Equivalent Elmore delay for RLC trees.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 83-97 (2000) |
| 1999 |
|---|
| 10 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Equivalent Elmore Delay for RLC Trees.
DAC 1999: 715-720 |
| 9 | EE | Yehea I. Ismail,
Eby G. Friedman:
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits.
DAC 1999: 721-724 |
| 8 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Inductance Effects in RLC Trees.
Great Lakes Symposium on VLSI 1999: 56-59 |
| 7 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Repeater insertion in tree structured inductive interconnect.
ICCAD 1999: 420-424 |
| 6 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Signal waveform characterization in RLC trees.
ISCAS (6) 1999: 190-193 |
| 5 | EE | Yehea I. Ismail,
Eby G. Friedman:
Repeater insertion in RLC lines for minimum propagation delay.
ISCAS (6) 1999: 404-407 |
| 4 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Figures of merit to characterize the importance of on-chip inductance.
IEEE Trans. VLSI Syst. 7(4): 442-449 (1999) |
| 1998 |
|---|
| 3 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Figures of Merit to Characterize the Importance of On-Chip Inductance.
DAC 1998: 560-565 |
| 2 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines.
Great Lakes Symposium on VLSI 1998: 39-44 |
| 1 | EE | Yehea I. Ismail,
Eby G. Friedman,
José Luis Neves:
Power dissipated by CMOS gates driving lossless transmission lines.
ISLPED 1998: 139-142 |
