2009 | ||
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119 | EE | Mainak Banga, Michael S. Hsiao: A Novel Sustained Vector Technique for the Detection of Hardware Trojans. VLSI Design 2009: 327-332 |
2008 | ||
118 | EE | Yexin Zheng, Michael S. Hsiao, Chao Huang: SAT-based equivalence checking of threshold logic designs for nanotechnologies. ACM Great Lakes Symposium on VLSI 2008: 225-230 |
117 | EE | Mainak Banga, Maheshwar Chandrasekar, Lei Fang, Michael S. Hsiao: Guided test generation for isolation and detection of embedded trojans in ics. ACM Great Lakes Symposium on VLSI 2008: 363-366 |
116 | EE | Lei Fang, Michael S. Hsiao: A Fast Approximation Algorithm for MIN-ONE SAT. DATE 2008: 1087-1090 |
115 | EE | Weixin Wu, Michael S. Hsiao: Efficient Design Validation Based on Cultural Algorithms. DATE 2008: 402-407 |
114 | EE | Xueqi Cheng, Michael S. Hsiao: Simulation-Directed Invariant Mining for Software Verification. DATE 2008: 682-687 |
113 | EE | Mainak Banga, Michael S. Hsiao: A Region Based Approach for the Identification of Hardware Trojans. HOST 2008: 40-47 |
112 | EE | Xueqi Cheng, Michael S. Hsiao: Ant Colony Optimization directed program abstraction for software bounded model checking. ICCD 2008: 46-51 |
111 | EE | Shrirang M. Yardi, Michael S. Hsiao: Quantifying the energy efficiency of coordinated micro-architectural adaptation for multimedia workloads. ICCD 2008: 583-590 |
110 | Karthik Channakeshava, Kaigui Bian, Michael S. Hsiao, Jung Min Park, Robert E. Crossler, France Belanger, Payal Aggarwal, Janine Hiller: On Providing Automatic Parental Consent over Information Collection from Children. Security and Management 2008: 196-202 | |
109 | EE | Michael S. Hsiao, Robert B. Jones: Introduction to special section on high-level design, validation, and test. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008) |
108 | EE | Weixin Wu, Michael S. Hsiao: Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 197-201 (2008) |
107 | EE | Lei Fang, Michael S. Hsiao: Bilateral Testing of Nano-scale Fault-Tolerant Circuits. J. Electronic Testing 24(1-3): 285-296 (2008) |
106 | EE | Hong-Sik Kim, Sungho Kang, Michael S. Hsiao: A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment. J. Electronic Testing 24(4): 365-378 (2008) |
2007 | ||
105 | EE | Lei Fang, Michael S. Hsiao: A new hybrid solution to boost SAT solver performance. DATE 2007: 1307-1313 |
104 | EE | Nannan He, Michael S. Hsiao: Bounded model checking of embedded software in wireless cognitive radio systems. ICCD 2007: 19-24 |
103 | EE | Vishnu C. Vimjam, Michael S. Hsiao: Explicit Safety Property Strengthening in SAT-based Induction. VLSI Design 2007: 63-68 |
102 | EE | Vishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang: Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. VTS 2007: 231-238 |
101 | EE | Xiaoding Chen, Michael S. Hsiao: An Overlapping Scan Architecture for Reducing Both Test Time and Test Power by Pipelining Fault Detection. IEEE Trans. VLSI Syst. 15(4): 404-412 (2007) |
2006 | ||
100 | EE | Vishnu C. Vimjam, Michael S. Hsiao: Fast illegal state identification for improving SAT-based induction. DAC 2006: 241-246 |
99 | EE | Weixin Wu, Michael S. Hsiao: Mining global constraints for improving bounded sequential equivalence checking. DAC 2006: 743-748 |
98 | EE | Lei Fang, Michael S. Hsiao: Bilateral Testing of Nano-scale Fault-tolerant Circuits. DFT 2006: 309-317 |
97 | EE | Kameshwar Chandrasekar, Michael S. Hsiao: Implicit Search-Space Aware Cofactor Expansion: A Novel Preimage Computation Technique. ICCD 2006 |
96 | EE | Vishnu C. Vimjam, Michael S. Hsiao: Efficient Fault Collapsing via Generalized Dominance Relations. VTS 2006: 258-265 |
95 | EE | Qingwei Wu, Michael S. Hsiao: A New Simulation-Based Property Checking Algorithm Based on Partitioned Alternative Search Space Traversal. IEEE Trans. Computers 55(11): 1325-1334 (2006) |
94 | EE | Xiaoding Chen, Michael S. Hsiao: Testing Embedded Sequential Cores in Parallel Using Spectrum-Based BIST. IEEE Trans. Computers 55(2): 150-162 (2006) |
93 | EE | Qingwei Wu, Michael S. Hsiao: State Variable Extraction and Partitioning to Reduce Problem Complexity for ATPG and Design Validation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2275-2282 (2006) |
92 | EE | Liang Zhang, Indradeep Ghosh, Michael S. Hsiao: A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2526-2538 (2006) |
91 | EE | Manan Syal, Michael S. Hsiao: New techniques for untestable fault identification in sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1117-1131 (2006) |
2005 | ||
90 | EE | Vishnu C. Vimjam, Manan Syal, Michael S. Hsiao: Untestable fault identification through enhanced necessary value assignments. ACM Great Lakes Symposium on VLSI 2005: 176-181 |
89 | EE | Ronald P. Lajaunie, Michael S. Hsiao: An effective and efficient ATPG-based combinational equivalence checker. ACM Great Lakes Symposium on VLSI 2005: 248-253 |
88 | EE | Kameshwar Chandrasekar, Michael S. Hsiao: Forward image computation with backtracing ATPG and incremental state-set construction. ACM Great Lakes Symposium on VLSI 2005: 254-259 |
87 | EE | Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty: Untestable Multi-Cycle Path Delay Faults in Industrial Designs. Asian Test Symposium 2005: 194-201 |
86 | EE | Liang Zhang, Mukul R. Prasad, Michael S. Hsiao: Interleaved Invariant Checking with Dynamic Abstraction. CHARME 2005: 81-96 |
85 | EE | Liang Zhang, Mukul R. Prasad, Michael S. Hsiao, Thomas Sidle: Dynamic abstraction using SAT-based BMC. DAC 2005: 754-757 |
84 | EE | Kameshwar Chandrasekar, Michael S. Hsiao: Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation. DATE 2005: 1002-1007 |
83 | EE | Shrirang M. Yardi, Michael S. Hsiao, Thomas L. Martin, Dong S. Ha: Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing. DATE 2005: 340-345 |
82 | EE | Shrirang M. Yardi, Karthik Channakeshava, Michael S. Hsiao, Thomas L. Martin, Dong S. Ha: A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management. ICCD 2005: 119-126 |
81 | EE | Manan Syal, Rajat Arora, Michael S. Hsiao: Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults. ICCD 2005: 453-460 |
80 | EE | Kameshwar Chandrasekar, Michael S. Hsiao: State Set Management for SAT-based Unbounded Model Checking. ICCD 2005: 585-590 |
79 | EE | Xueqi Cheng, Michael S. Hsiao: Region-level approximate computation reuse for power reduction in multimedia applications. ISLPED 2005: 119-122 |
78 | EE | Daniel C. Nash, Thomas L. Martin, Dong S. Ha, Michael S. Hsiao: Towards an Intrusion Detection System for Battery Exhaustion Attacks on Mobile Computing Devices. PerCom Workshops 2005: 141-145 |
77 | EE | Kameshwar Chandrasekar, Michael S. Hsiao: Q-PREZ: QBF Evaluation Using Partition, Resolution and Elimination with ZBDDs. VLSI Design 2005: 189-194 |
76 | EE | Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Efficient techniques for transition testing. ACM Trans. Design Autom. Electr. Syst. 10(2): 258-278 (2005) |
75 | EE | Xiao Liu, Michael S. Hsiao: A Novel Transition Fault ATPG That Reduces Yield Loss. IEEE Design & Test of Computers 22(6): 576-584 (2005) |
74 | EE | Anand L. D'Souza, Michael S. Hsiao: Error Diagnosis of Sequential Circuits Using Region-Based Model. J. Electronic Testing 21(2): 115-126 (2005) |
2004 | ||
73 | EE | Bin Li, Michael S. Hsiao, Shuo Sheng: A Novel SAT All-Solutions Solver for Efficient Preimage Computation. DATE 2004: 272-279 |
72 | EE | Liang Zhang, Mukul R. Prasad, Michael S. Hsiao: Incremental deductive & inductive reasoning for SAT-based bounded model checking. ICCAD 2004: 502-509 |
71 | EE | Manan Syal, Michael S. Hsiao, Sreejit Chakravarty: Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. ITC 2004: 1034-1043 |
70 | EE | Puneet Gupta, Michael S. Hsiao: ALAPTF: A new Transition Faultmodel and the ATPG Algorithm. ITC 2004: 1053-1060 |
69 | EE | Kameshwar Chandrasekar, Michael S. Hsiao: Decision Selection and Learning for an All-Solutions ATPG Engine. ITC 2004: 607-616 |
68 | EE | Qingwei Wu, Michael S. Hsiao: State Variable Extraction to Reduce Problem Complexity for ATPG and Design Validation. ITC 2004: 820-829 |
67 | EE | Thomas L. Martin, Michael S. Hsiao, Dong S. Ha, Jayan Krishnaswami: Denial-of-Service Attacks on Battery-powered Mobile Computers. PerCom 2004: 309-318 |
66 | EE | Manan Syal, Michael S. Hsiao: Untestable Fault Identification using Recurrence Relations and Impossible Value Assignments. VLSI Design 2004: 481-486 |
65 | EE | Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain: Can SAT be used to Improve Sequential ATPG Methods? VLSI Design 2004: 585- |
64 | EE | Rajat Arora, Michael S. Hsiao: Enhancing SAT-based Bounded Model Checking using Sequential Logic Implications. VLSI Design 2004: 784-787 |
63 | EE | Qingwei Wu, Michael S. Hsiao: Efficient ATPG for Design Validation Based On Partitioned State Exploration Histories. VTS 2004: 389-405 |
62 | EE | Shuo Sheng, Michael S. Hsiao: Success-Driven Learning in ATPG for Preimage Computation. IEEE Design & Test of Computers 21(6): 504-512 (2004) |
61 | EE | Rajat Arora, Michael S. Hsiao: Using Global Structural Relationships of Signals to Accelerate SAT-based Combinational Equivalence Checking. J. UCS 10(12): 1597-1628 (2004) |
2003 | ||
60 | EE | Liang Zhang, Michael S. Hsiao, Indradeep Ghosh: Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. Asian Test Symposium 2003: 148-153 |
59 | EE | Manan Syal, Michael S. Hsiao: A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification. DATE 2003: 10316-10321 |
58 | EE | Shuo Sheng, Michael S. Hsiao: Efficient Preimage Computation Using A Novel Success-Driven ATPG. DATE 2003: 10822-10827 |
57 | EE | Xiao Liu, Michael S. Hsiao: Constrained ATPG for Broadside Transition Testing. DFT 2003: 175- |
56 | EE | Qingwei Wu, Michael S. Hsiao: Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal. ITC 2003: 281-289 |
55 | EE | Liang Zhang, Indradeep Ghosh, Michael S. Hsiao: Efficient Sequential ATPG for Functional RTL Circuits. ITC 2003: 290-298 |
54 | EE | Puneet Gupta, Michael S. Hsiao: High Quality ATPG for Delay Defects. ITC 2003: 584-591 |
53 | EE | Xiaoding Chen, Michael S. Hsiao: Energy-Efficient Logic BIST Based on State Correlation Analysis. VTS 2003: 267-272 |
52 | EE | Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty: Efficient Implication - Based Untestable Bridge Fault Identifier. VTS 2003: 393-402 |
51 | EE | Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors. J. Electronic Testing 19(4): 437-445 (2003) |
2002 | ||
50 | EE | Shuo Sheng, Koichiro Takayama, Michael S. Hsiao: Effective safety property checking using simulation-based sequential ATPG. DAC 2002: 813-818 |
49 | EE | Michael S. Hsiao: Maximizing Impossibilities for Untestable Fault Identification. DATE 2002: 949-953 |
48 | EE | Xiaoding Chen, Michael S. Hsiao: Characteristic faults and spectral information for logic BIST. ICCAD 2002: 294-298 |
47 | EE | Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran: Techniques to Reduce Data Volume and Application Time for Transition Test. ITC 2002: 983-992 |
46 | Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain: Improving Sequential ATPG Using SAT Methods. IWLS 2002: 79-84 | |
45 | EE | Yufeng Zhao, Michael S. Hsiao: Reducing Power Consumption by Utilizing Retransmission in Short Range Wireless Network. LCN 2002: 527-533 |
44 | EE | Phillip Stanley-Marbell, Michael S. Hsiao, Ulrich Kremer: A Hardware Architecture for Dynamic Performance and Energy Adaptation. PACS 2002: 33-52 |
43 | EE | Ganapathy Kasturirangan, Michael S. Hsiao: Spectrum-Based BIST in Complex SOCs. VTS 2002: 111-116 |
42 | EE | Shuo Sheng, Michael S. Hsiao: Efficient Sequential Test Generation Based on Logic Simulation. IEEE Design & Test of Computers 19(5): 56-64 (2002) |
41 | EE | Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: State and Fault Information for Compaction-Based Test Generation. J. Electronic Testing 18(1): 63-72 (2002) |
40 | EE | Sandhya Seshadri, Michael S. Hsiao: Behavioral-Level DFT via Formal Operator Testability Measures. J. Electronic Testing 18(6): 595-611 (2002) |
2001 | ||
39 | EE | Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: Efficient spectral techniques for sequential ATPG. DATE 2001: 204-208 |
38 | EE | Phillip Stanley-Marbell, Michael S. Hsiao: Fast, flexible, cycle-accurate energy estimation. ISLPED 2001: 141-146 |
37 | EE | Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao: Compiler-directed dynamic voltage/frequency scheduling for energy reduction in mircoprocessors. ISLPED 2001: 275-278 |
36 | Nandini Sridhar, Michael S. Hsiao: On efficient error diagnosis of digital circuits. ITC 2001: 678-687 | |
35 | EE | Anand L. D'Souza, Michael S. Hsiao: Error Diagnosis of Sequential Circuits Using Region-Based Mode. VLSI Design 2001: 103- |
34 | EE | Sameer Sharma, Michael S. Hsiao: Combination of Structural and State Analysis for Partial Scan. VLSI Design 2001: 134- |
33 | EE | Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar: Accurate Power Macro-modeling Techniques for Complex RTL Circuits. VLSI Design 2001: 235-241 |
32 | EE | Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. VTS 2001: 163-168 |
31 | Matthew Arnold, Michael S. Hsiao, Ulrich Kremer, Barbara G. Ryder: Exploring the Interaction between Java?s Implicitly Thrown Exceptions and Instruction Scheduling. International Journal of Parallel Programming 29(2): 111-137 (2001) | |
2000 | ||
30 | EE | Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: Compaction-based test generation using state and fault information. Asian Test Symposium 2000: 159-164 |
29 | EE | Ruofan Xu, Michael S. Hsiao: Embedded core testing using genetic algorithms. Asian Test Symposium 2000: 254-259 |
28 | EE | Kabir Gulrajani, Michael S. Hsiao: Multi-Node Static Logic Implications for Redundancy Identification. DATE 2000: 729- |
27 | EE | Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao: Compiler-Directed Dynamic Frequency and Voltage Scheduling. PACS 2000: 65-81 |
26 | EE | Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao: Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS 2000: 263-270 |
25 | EE | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Dynamic state traversal for sequential circuit test generation. ACM Trans. Design Autom. Electr. Syst. 5(3): 548-565 (2000) |
24 | EE | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Peak power estimation of VLSI circuits: new peak power measures. IEEE Trans. VLSI Syst. 8(4): 435-439 (2000) |
23 | EE | Sandhya Seshadri, Michael S. Hsiao: Formal Value-Range and Variable Testability Techniques for High-Level Design-For-Testability. J. Electronic Testing 16(1-2): 131-145 (2000) |
22 | EE | Michael S. Hsiao, Srimat T. Chakradhar: Test Set Compaction Using Relaxed Subsequence Removal. J. Electronic Testing 16(4): 319-327 (2000) |
21 | EE | Michael S. Hsiao, Srimat T. Chakradhar: Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits. J. Electronic Testing 16(4): 329-338 (2000) |
1999 | ||
20 | EE | Michael S. Hsiao: Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits. DATE 1999: 175- |
19 | Sandhya Seshadri, Michael S. Hsiao: An integrated approach to behavioral-level design-for-testability using value-range and variable testability techniques. ITC 1999: 858-867 | |
18 | EE | Matthew Arnold, Michael S. Hsiao, Ulrich Kremer, Barbara G. Ryder: Instruction Scheduling in the Presence of Java's Runtime Exceptions. LCPC 1999: 18-34 |
17 | EE | Sameer Sharma, Michael S. Hsiao: Partial Scan Using Multi-Hop State Reachability Analysis. VTS 1999: 121-127 |
16 | EE | Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita: On the Evaluation of Arbitrary Defect Coverage of Test Sets. VTS 1999: 426-432 |
15 | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Fast Static Compaction Algorithms for Sequential Circuit Test Vectors. IEEE Trans. Computers 48(3): 311-322 (1999) | |
14 | EE | Michael S. Hsiao: On Non-Statistical Techniques for Fast Fault Coverage Estimation. J. Electronic Testing 15(3): 239-254 (1999) |
1998 | ||
13 | EE | Michael S. Hsiao, Srimat T. Chakradhar: Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits. Asian Test Symposium 1998: 452-457 |
12 | EE | Michael S. Hsiao, Srimat T. Chakradhar: State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits. DATE 1998: 577-582 |
11 | EE | Michael S. Hsiao: A fast, accurate, and non-statistical method for fault coverage estimation. ICCAD 1998: 155-161 |
10 | EE | Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel: Partial Scan Selection Based on Dynamic Reachability and Observability Information. VLSI Design 1998: 174-180 |
9 | EE | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 239-254 (1998) |
1997 | ||
8 | EE | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Sequential circuit test generation using dynamic state traversal. ED&TC 1997: 22-28 |
7 | Gurjeet S. Saund, Michael S. Hsiao, Janak H. Patel: Partial Scan beyond Cycle Cutting. FTCS 1997: 320-328 | |
6 | EE | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Effects of delay models on peak power estimation of VLSI sequential circuits. ICCAD 1997: 45-51 |
5 | EE | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: K2: an estimator for peak sustainable power of VLSI circuits. ISLPED 1997: 178-183 |
4 | EE | Dilip Krishnaswamy, Michael S. Hsiao, Vikram Saxena, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee: Parallel Genetic Algorithms for Simulation-Based Sequential Circuit Test Generation. VLSI Design 1997: 475-481 |
3 | EE | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. VTS 1997: 188-195 |
1996 | ||
2 | EE | Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel: Automatic test generation using genetically-engineered distinguishing sequences. VTS 1996: 216-223 |
1995 | ||
1 | EE | Michael S. Hsiao, Janak H. Patel: A new architectural-level fault simulation using propagation prediction of grouped fault-effects. ICCD 1995: 628- |