Tung-Chieh Chen

2008
16	EE	Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan: An integrated nonlinear placement framework with congestion and porosity aware buffer planning. DAC 2008: 702-707
15	EE	Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-density driven placement for cmp variation and routability. ISPD 2008: 31-38
14	EE	Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang: Metal-Density-Driven Placement for CMP Variation and Routability. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2145-2155 (2008)
13	EE	Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin: A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 286-294 (2008)
12	EE	Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang: Effective Wire Models for X-Architecture Placement. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 654-658 (2008)
11	EE	Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang: NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1228-1240 (2008)
10	EE	Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu: MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1621-1634 (2008)
2007
9	EE	Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu: MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. DAC 2007: 447-452
8	EE	Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang: X-architecture placement based on effective wire models. ISPD 2007: 87-94
2006
7	EE	Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang: A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. ICCAD 2006: 187-192
6	EE	Zhe-Wei Jiang, Tung-Chieh Chen, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang: NTUplace2: a hybrid placer using partitioning and analytical techniques. ISPD 2006: 215-217
5	EE	Tung-Chieh Chen, Yao-Wen Chang: Modern Floorplanning Based on B*-Tree and Fast Simulated Annealing. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 637-650 (2006)
2005
4	EE	Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang: SoC test scheduling using the B-tree based floorplanning technique. ASP-DAC 2005: 1188-1191
3		Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin: IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. ICCAD 2005: 159-164
2	EE	Tung-Chieh Chen, Yao-Wen Chang: Modern floorplanning based on fast simulated annealing. ISPD 2005: 104-112
1	EE	Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang: NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs. ISPD 2005: 236-238

Coauthor Index

1	Ashutosh Chakraborty	[16]
2	Yao-Wen Chang	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]
3	Hsin-Chen Chen	[6] [7] [11]
4	Minsik Cho	[14] [15]
5	Yi-Lin Chuang	[8] [12]
6	Tien-Chang Hsu	[1] [6] [7] [11]
7	Few-Juh Huang	[10]
8	Fwu-Juh Huang	[9]
9	Zhe-Wei Jiang	[1] [6] [7] [11]
10	Shyh-Chang Lin	[3] [13]
11	Denny Liu	[9]
12	T.-Y. Liu	[10]
13	David Z. Pan (David Zhigang Pan)	[14] [15] [16]
14	Jen-Yi Wuu	[4]
15	Ping-Hung Yuh	[9] [10]