Ruifeng Guo

2008
18	EE	Wanfu Ding, Ruifeng Guo: Design and Evaluation of Sectional Real-Time Scheduling Algorithms Based on System Load. ICYCS 2008: 14-18
2007
17	EE	Vishnu C. Vimjam, Enamul Amyeen, Ruifeng Guo, Srikanth Venkataraman, Michael S. Hsiao, Kai Yang: Using Scan-Dump Values to Improve Functional-Diagnosis Methodology. VTS 2007: 231-238
2006
16	EE	Ruifeng Guo, Subhasish Mitra, Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman: Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive. VTS 2006: 66-71
15	EE	Ruifeng Guo, Srikanth Venkataraman: An algorithmic technique for diagnosis of faulty scan chains. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1861-1868 (2006)
2005
14	EE	Dong Yu, Hu Lin, Ruifeng Guo, Jiangang Yang, Pengfei Xiao: The Research on Real-Time Middleware for Open Architecture Controller. RTCSA 2005: 80-83
2004
13	EE	Srikanth Venkataraman, Srihari Sivaraj, Enamul Amyeen, Sangbong Lee, Ajay Ojha, Ruifeng Guo: An Experimental Study of N-Detect Scan ATPG Patterns on a Processor. VTS 2004: 23-30
2003
12	EE	Xiaoming Yu, Enamul Amyeen, Srikanth Venkataraman, Ruifeng Guo, Irith Pomeranz: Concurrent Execution of Diagnostic Fault Simulation and Equivalence Identification During Diagnostic Test Generation. VTS 2003: 351-358
11	EE	Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: Reverse-order-restoration-based static test compaction for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 293-304 (2003)
10	EE	Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: PROPTEST: a property-based test generator for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1080-1091 (2003)
2001
9	EE	Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. Asian Test Symposium 2001: 82-
8		Ruifeng Guo, Srikanth Venkataraman: A technique for fault diagnosis of defects in scan chains. ITC 2001: 268-277
7	EE	Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy: On Improving Static Test Compaction for Sequential Circuits. VLSI Design 2001: 111-116
1999
6	EE	Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. DAC 1999: 653-659
5		Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz: The effects of test compaction on fault diagnosis. ITC 1999: 1083-1089
4	EE	Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy: A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. VTS 1999: 260-267
3	EE	Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo: Static test compaction for synchronous sequential circuits based on vector restoration. IEEE Trans. on CAD of Integrated Circuits and Systems 18(7): 1040-1049 (1999)
1998
2	EE	Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy: On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . Asian Test Symposium 1998: 467-471
1	EE	Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy: Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. DATE 1998: 583-

Coauthor Index

1	Enamul Amyeen	[12] [13] [16] [17]
2	Wanfu Ding	[18]
3	Michael S. Hsiao	[17]
4	Jinkyu Lee	[16]
5	Sangbong Lee	[13]
6	Hu Lin	[14]
7	Subhasish Mitra	[16]
8	Ajay Ojha	[13]
9	Irith Pomeranz	[1] [2] [3] [4] [5] [6] [7] [9] [10] [11] [12]
10	Sudhakar M. Reddy	[1] [2] [3] [4] [5] [6] [7] [9] [10] [11]
11	Yun Shao	[5]
12	Srihari Sivaraj	[13] [16]
13	Srikanth Venkataraman	[8] [12] [13] [15] [16] [17]
14	Vishnu C. Vimjam	[17]
15	Pengfei Xiao	[14]
16	Jiangang Yang	[14]
17	Kai Yang	[17]
18	Dong Yu	[14]
19	Xiaoming Yu	[12]

Colors in the list of coauthors