| 2009 |
|---|
| 20 | EE | Mehrdad Reshadi,
Prabhat Mishra,
Nikil D. Dutt:
Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulation.
ACM Trans. Embedded Comput. Syst. 8(3): (2009) |
| 2008 |
|---|
| 19 | EE | Mehrdad Reshadi,
Bita Gorjiara,
Daniel Gajski:
C-based design flow: a case study on G.729A for voice over internet protocol (VoIP).
DAC 2008: 72-75 |
| 18 | EE | Bita Gorjiara,
Mehrdad Reshadi,
Daniel Gajski:
Merged Dictionary Code Compression for FPGA Implementation of Custom Microcoded PEs.
TRETS 1(2): (2008) |
| 2007 |
|---|
| 17 | EE | Mehrdad Reshadi,
Daniel Gajski:
Interrupt and low-level programming support for expanding the application domain of statically-scheduled horizontal-microcoded architectures in embedded systems.
DATE 2007: 1337-1342 |
| 16 | EE | Mehrdad Reshadi,
Nikil Dutt:
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation
CoRR abs/0710.4643: (2007) |
| 2006 |
|---|
| 15 | EE | Bita Gorjiara,
Mehrdad Reshadi,
Daniel D. Gajski:
Designing a custom architecture for DCT using NISC technology.
ASP-DAC 2006: 116-117 |
| 14 | EE | Bita Gorjiara,
Mehrdad Reshadi,
Pramod Chandraiah,
Daniel Gajski:
Generic netlist representation for system and PE level design exploration.
CODES+ISSS 2006: 282-287 |
| 13 | EE | Jelena Trajkovic,
Mehrdad Reshadi,
Bita Gorjiara,
Daniel Gajski:
A Graph Based Algorithm for Data Path Optimization in Custom Processors.
DSD 2006: 496-503 |
| 12 | EE | Bita Gorjiara,
Mehrdad Reshadi,
Daniel Gajski:
Aspect-Oriented Architecture Description for Retargetable Compilation, Simulation and Synthesis of Application-Specific Pipelined Datapaths .
ICCD 2006 |
| 11 | EE | Mehrdad Reshadi,
Nikil Dutt,
Prabhat Mishra:
A retargetable framework for instruction-set architecture simulation.
ACM Trans. Embedded Comput. Syst. 5(2): 431-452 (2006) |
| 10 | EE | Mehrdad Reshadi,
Bita Gorjiara,
Nikil D. Dutt:
Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate Simulators.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2904-2918 (2006) |
| 2005 |
|---|
| 9 | EE | Mehrdad Reshadi,
Daniel Gajski:
A cycle-accurate compilation algorithm for custom pipelined datapaths.
CODES+ISSS 2005: 21-26 |
| 8 | EE | Mehrdad Reshadi,
Prabhat Mishra:
Memory access optimizations in instruction-set simulators.
CODES+ISSS 2005: 237-242 |
| 7 | EE | Mehrdad Reshadi,
Nikil D. Dutt:
Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation.
DATE 2005: 786-791 |
| 6 | EE | Mehrdad Reshadi,
Bita Gorjiara,
Daniel D. Gajski:
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths.
ICCD 2005: 69-76 |
| 2004 |
|---|
| 5 | EE | Bita Gorjiara,
Pai H. Chou,
Nader Bagherzadeh,
Mehrdad Reshadi,
David Jensen:
Fast and efficient voltage scheduling by evolutionary slack distribution.
ASP-DAC 2004: 659-662 |
| 2003 |
|---|
| 4 | EE | Mehrdad Reshadi,
Nikhil Bansal,
Prabhat Mishra,
Nikil D. Dutt:
An efficient retargetable framework for instruction-set simulation.
CODES+ISSS 2003: 13-18 |
| 3 | EE | Mehrdad Reshadi,
Prabhat Mishra,
Nikil D. Dutt:
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation.
DAC 2003: 758-763 |
| 2 | EE | Mehrdad Reshadi,
Nikil D. Dutt:
Reducing Compilation Time Overhead in Compiled Simulators.
ICCD 2003: 151- |
| 2002 |
|---|
| 1 | EE | Alexandru Nicolau,
Nikil D. Dutt,
Rajesh Gupta,
Nick Savoiu,
Mehrdad Reshadi,
Sumit Gupta:
Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis.
ISSS 2002: 261-266 |
