| 2009 |
|---|
| 21 | EE | Alan Mishchenko,
Robert K. Brayton,
Jie-Hong Roland Jiang,
Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis.
FPGA 2009: 151-160 |
| 2008 |
|---|
| 20 | EE | Ruei-Rung Lee,
Jie-Hong Roland Jiang,
Wei-Lun Hung:
Bi-decomposing large Boolean functions via interpolation and satisfiability solving.
DAC 2008: 636-641 |
| 19 | EE | Hsuan-Po Lin,
Jie-Hong Roland Jiang,
Ruei-Rung Lee:
To SAT or not to SAT: Ashenhurst decomposition in a large scale.
ICCAD 2008: 32-37 |
| 18 | EE | Sz-Cheng Huang,
Jie-Hong Roland Jiang:
A dynamic accuracy-refinement approach to timing-driven technology mapping.
ICCD 2008: 538-543 |
| 2007 |
|---|
| 17 | EE | Chih-Chun Lee,
Jie-Hong Roland Jiang,
Chung-Yang Huang,
Alan Mishchenko:
Scalable exploration of functional dependency by interpolation and incremental SAT solving.
ICCAD 2007: 227-233 |
| 16 | EE | Jie-Hong Roland Jiang,
Wei-Lun Hung:
Inductive equivalence checking under retiming and resynthesis.
ICCAD 2007: 326-333 |
| 15 | EE | Chin-Hsiung Hsu,
Szu-Jui Chou,
Jie-Hong Roland Jiang,
Yao-Wen Chang:
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits.
PATMOS 2007: 148-159 |
| 14 | EE | Alan Mishchenko,
Robert K. Brayton,
Jie-Hong Roland Jiang,
Tiziano Villa,
Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations
CoRR abs/0710.4743: (2007) |
| 2006 |
|---|
| 13 | EE | Jie-Hong Roland Jiang,
Robert K. Brayton:
Retiming and Resynthesis: A Complexity Perspective.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2674-2686 (2006) |
| 2005 |
|---|
| 12 | EE | Alan Mishchenko,
Robert K. Brayton,
Jie-Hong Roland Jiang,
Tiziano Villa,
Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations.
DATE 2005: 418-423 |
| 11 | EE | Jie-Hong Roland Jiang:
On Some Transformation Invariants Under Retiming and Resynthesis.
TACAS 2005: 413-428 |
| 2004 |
|---|
| 10 | EE | Jie-Hong Roland Jiang,
Robert K. Brayton:
Functional Dependency for Verification Reduction.
CAV 2004: 268-280 |
| 9 | EE | Jie-Hong Roland Jiang,
Alan Mishchenko,
Robert K. Brayton:
On breakable cyclic definitions.
ICCAD 2004: 411-418 |
| 2003 |
|---|
| 8 | EE | Jie-Hong Roland Jiang,
Alan Mishchenko,
Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary.
DATE 2003: 10752-10757 |
| 7 | EE | Jie-Hong Roland Jiang,
Robert K. Brayton:
On the verification of sequential equivalence.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 686-697 (2003) |
| 2002 |
|---|
| 6 | EE | Robert K. Brayton,
M. Gao,
Jie-Hong Roland Jiang,
Yunjian Jiang,
Yinghua Li,
Alan Mishchenko,
Subarnarekha Sinha,
Tiziano Villa:
Optimization of Multi-Valued Multi-Level Networks.
ISMVL 2002: 168- |
| 5 | | Jie-Hong Roland Jiang,
Robert K. Brayton:
On the Verification of Sequential Equivalence.
IWLS 2002: 307-314 |
| 4 | | Jie-Hong Roland Jiang,
Alan Mishchenko,
Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary.
IWLS 2002: 339-344 |
| 2001 |
|---|
| 3 | EE | Jie-Hong Roland Jiang,
Jing-Yang Jou,
Juinn-Dar Huang:
Unified functional decomposition via encoding for FPGA technology mapping.
IEEE Trans. VLSI Syst. 9(2): 251-260 (2001) |
| 1999 |
|---|
| 2 | EE | Jie-Hong Roland Jiang,
Iris Hui-Ru Jiang:
Optimum loading dispersion for high-speed tree-type decision circuitry.
ICCAD 1999: 520-525 |
| 1998 |
|---|
| 1 | EE | Jie-Hong Roland Jiang,
Jing-Yang Jou,
Juinn-Dar Huang:
Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis.
DAC 1998: 712-717 |
