Zeljko Zilic

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54EEM. H. Neishabouri, Zeljko Zilic: Reliability aware NoC router architecture using input channel buffer sharing. ACM Great Lakes Symposium on VLSI 2009: 511-516
53EEYann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic: MYGEN: automata-based on-line test generator for assertion-based verification. ACM Great Lakes Symposium on VLSI 2009: 75-80
52EEYongquan Fan, Zeljko Zilic: Accelerating jitter tolerance qualification for high speed serial interfaces. ISQED 2009: 360-365
51EEAtanu Chattopadhyay, Zeljko Zilic: Built-in Clock Skew System for On-line Debug and Repair. DATE 2008: 248-251
50EEMarc Boule, Zeljko Zilic: Automata-based assertion-checker synthesis of PSL properties. ACM Trans. Design Autom. Electr. Syst. 13(1): (2008)
49EEStephan Bourduas, Zeljko Zilic: Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing. ASAP 2007: 302-307
48EEMarc Boule, Zeljko Zilic: Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation. ASP-DAC 2007: 324-329
47EEHenry H. Y. Chan, Zeljko Zilic: Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops. DAC 2007: 430-435
46EEZeljko Zilic, Katarzyna Radecka, Ali Kazamiphur: Reversible circuit technology mapping from non-reversible specifications. DATE 2007: 558-563
45EEHenry H. Y. Chan, Zeljko Zilic: A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits. ISCAS 2007: 2934-2937
44EEAtanu Chattopadhyay, Zeljko Zilic: Reconfigurable Clock Distribution Circuitry. ISCAS 2007: 877-880
43EEMarc Boule, Jean-Samuel Chenard, Zeljko Zilic: Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis. ISQED 2007: 613-620
42EEStephan Bourduas, Zeljko Zilic: A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing. NOCS 2007: 195-204
41EEZeljko Zilic, Katarzyna Radecka: Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. IEEE Trans. Computers 56(2): 202-207 (2007)
40EEMarc Boule, Jean-Samuel Chenard, Zeljko Zilic: Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug. ICCD 2006
39EERong Zhang, Zeljko Zilic, Katarzyna Radecka: Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. VTS 2006: 186-191
38EEKnockaert Radecka, Zeljko Zilic: Arithmetic transforms for compositions of sequential and imprecise datapaths. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1382-1391 (2006)
37EEJean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic: Design methodology for wireless nodes with printed antennas. DAC 2005: 291-296
36EEMarc Boule, Zeljko Zilic: Incorporating Ef.cient Assertion Checkers into Hardware Emulation. ICCD 2005: 221-228
35EEHenry H. Y. Chan, Zeljko Zilic: Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization. ISQED 2005: 390-395
34EEJean-Samuel Chenard, Ahmed Usman Khalid, M. Prokic, Rong Zhang, K.-L. Lim, Atanu Chattopadhyay, Zeljko Zilic: Expandable and Robust Laboratory for Microprocessor Systems. MSE 2005: 65-66
33EEAtanu Chattopadhyay, Zeljko Zilic: GALDS: a complete framework for designing multiclock ASICs and SoCs. IEEE Trans. VLSI Syst. 13(6): 641-654 (2005)
32EEAhmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka: FPGA Emulation of Quantum Circuits. ICCD 2004: 310-315
31 Yongquan Fan, Zeljko Zilic: A novel scheme of implementing high speed AWGN communication channel emulators in FPGAs. ISCAS (2) 2004: 877-880
30EEHenry H. Y. Chan, Zeljko Zilic: Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach. ISQED 2004: 309-314
29EEYongquan Fan, Zeljko Zilic, Man Wah Chiang: A Versatile High Speed Bit Error Rate Testing Scheme. ISQED 2004: 395-400
28EEStuart McCracken, Zeljko Zilic: Design for Testability of FPGA Blocks. ISQED 2004: 86-91
27EEMan Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka: Architectures of Increased Availability Wireless Sensor Network Nodes. ITC 2004: 1232-1241
26EEKatarzyna Radecka, Zeljko Zilic: Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. IEEE Trans. Computers 53(5): 628-640 (2004)
25EEAtanu Chattopadhyay, Zeljko Zilic: A globally asynchronous locally dynamic system for ASICs and SoCs. ACM Great Lakes Symposium on VLSI 2003: 176-181
24EEYongquan Fan, Zeljko Zilic: Testing for bit error rate in FPGA communication interfaces. FPGA 2003: 243
23EEMan Wah Chiang, Zeljko Zilic: Layered Approach to Designing System Test Interfaces. VTS 2003: 331-338
22EEStuart McCracken, Zeljko Zilic: FPGA test time reduction through a novel interconnect testing scheme. FPGA 2002: 136-144
21EEKatarzyna Radecka, Zeljko Zilic: Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. ICCAD 2002: 128-131
20EEZeljko Zilic, Katarzyna Radecka: The Role of Super-Fast Transforms in Speeding Up Quantum Computations. ISMVL 2002: 129-135
19EEBoris Polianskikh, Zeljko Zilic: Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection. ISMVL 2002: 89-95
18EEKatarzyna Radecka, Zeljko Zilic: Identifying Redundant Wire Replacements for Synthesis and Verification. VLSI Design 2002: 517-523
17EEZeljko Zilic, Zvonko G. Vranesic: A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. IEEE Trans. Computers 51(9): 1100-1105 (2002)
16 Katarzyna Radecka, Zeljko Zilic: Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. ICCD 2001: 348-353
15EEIan Brynjolfson, Zeljko Zilic: A new PLL design for clock management applications. ISCAS (4) 2001: 814-817
14 Zeljko Zilic, Katarzyna Radecka: : Identifying redundant gate replacements in verification by error modeling. ITC 2001: 803-812
13EEIan Brynjolfson, Zeljko Zilic: FPGA clock management for low power applications (poster abstract). FPGA 2000: 219
12EER. Grindley, Tarek S. Abdelrahman, Stephen Dean Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: The NUMAchine Multiprocessor. ICPP 2000: 487-496
11EEKatarzyna Radecka, Zeljko Zilic: Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. VTS 2000: 271-280
10EEZeljko Zilic, Katarzyna Radecka: On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. ISSAC 1999: 67-74
9EEZeljko Zilic: Alternatives in Teaching System-Building Skills. MSE 1999: 57-58
8EEA. Grbic, Stephen Dean Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic: Design and Implementation of the NUMAchine Multiprocessor. DAC 1998: 66-69
7 Zeljko Zilic, Zvonko G. Vranesic: Using Decision Diagrams to Design ULMs for FPGAs. IEEE Trans. Computers 47(9): 970-982 (1998)
6EEStephen Dean Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic: Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. DAC 1996: 427-432
5EEZeljko Zilic, Zvonko G. Vranesic: Using BDDs to Design ULMs for FPGAs. FPGA 1996: 24-30
4EEZeljko Zilic, Zvonko G. Vranesic: New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. ISMVL 1996: 16-23
3EEZeljko Zilic, Zvonko G. Vranesic: Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. ISMVL 1995: 36-43
2 Zeljko Zilic, Zvonko G. Vranesic: A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. IEEE Trans. Computers 44(8): 1012-1020 (1995)
1 Zeljko Zilic, Zvonko G. Vranesic: Current-Mode CMOS Galois Field Circuits. ISMVL 1993: 245-250

Coauthor Index

1Tarek S. Abdelrahman [12]
2Dominique Borrione [53]
3Marc Boule [36] [40] [43] [48] [50] [53]
4Stephan Bourduas [42] [49]
5Stephen Dean Brown [6] [8] [12]
6Ian Brynjolfson [13] [15]
7S. Caranci [6] [8] [12]
8Henry H. Y. Chan [30] [35] [45] [47]
9Atanu Chattopadhyay [25] [33] [34] [44] [51]
10Jean-Samuel Chenard [27] [34] [37] [40] [43]
11Man Wah Chiang [23] [27] [29]
12Chun Yiu Chu [37]
13D. DeVries [12]
14Yongquan Fan [24] [29] [31] [52]
15Benjamin Gamsa [12]
16A. Grbic [6] [8] [12]
17R. Grindley [6] [8] [12]
18M. Gusat [6] [8] [12]
19R. Ho [12]
20Ali Kazamiphur [46]
21Ahmed Usman Khalid [32] [34]
22Orran Krieger [12]
23Guy G. Lemieux [8] [12]
24K.-L. Lim [34]
25K. Loveless [6] [8] [12]
26Naraig Manjikian [6] [8] [12]
27Stuart McCracken [22] [28]
28P. McHardy [12]
29Katell Morin-Allory [53]
30M. H. Neishabouri [54]
31Yann Oddos [53]
32Boris Polianskikh [19]
33Milica Popovic [37]
34M. Prokic [34]
35Katarzyna Radecka [10] [11] [14] [16] [18] [20] [21] [26] [27] [32] [39] [41] [46]
36Knockaert Radecka [38]
37Sinisa Srbljic [6] [8] [12]
38Michael Stumm [8] [12]
39Zvonko G. Vranesic [1] [2] [3] [4] [5] [6] [7] [8] [12] [17]
40Rong Zhang [34] [39]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)