Mustafa Badaroglu

2008
11	EE	Mustafa Badaroglu, Guy Decabooter, Francois Laulanet, Olivier Charlier: Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment. DATE 2008: 873-878
2007
10	EE	Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Scalable Gate-Level Models for Power and Timing Analysis. ISCAS 2007: 2938-2941
9	EE	Claude Desset, Mustafa Badaroglu, Julien Ryckaert, Bart van Poucke: Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers. VTC Spring 2007: 3135-3139
2006
8	EE	Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. VLSI Syst. 14(1): 23-33 (2006)
7	EE	Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1146-1154 (2006)
2005
6	EE	Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 65-76 (2005)
2004
5	EE	Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC 2004: 854-859
4	EE	Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE 2004: 88-93
2002
3	EE	Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen: Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC 2002: 399-404
2001
2	EE	Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens: High-level simulation of substrate noise generation from large digital circuits with multiple supplies. DATE 2001: 326-330
2000
1	EE	Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens: High-level simulation of substrate noise generation including power supply noise coupling. DAC 2000: 446-451

Coauthor Index

1	Ivo Bolsens	[1] [2]
2	Olivier Charlier	[11]
3	Guy Decabooter	[11]
4	Claude Desset	[9]
5	Petr Dobrovolný	[5]
6	Stéphane Donnay	[1] [2] [3] [4] [5] [6] [7] [8] [10]
7	Marc Engels	[1] [2]
8	Georges G. E. Gielen	[2] [3] [4] [5] [6] [7] [8] [10]
9	Vincent Gravot	[2]
10	Marc van Heijningen	[1] [2]
11	Francois Laulanet	[11]
12	Hugo De Man	[2] [3] [4] [5] [6] [7] [8] [10]
13	Geert Van der Plas	[4] [5] [6] [7] [8] [10]
14	Bart van Poucke	[9]
15	Julien Ryckaert	[9]
16	Kris Tiri	[3] [7]
17	Gerd Vandersteen	[5]
18	Ingrid Verbauwhede	[3] [7]
19	Piet Wambacq	[3] [4] [5] [6] [7] [8] [10]

Colors in the list of coauthors