| 2009 |
|---|
| 155 | EE | Nilanjan Banerjee,
Saumya Chandra,
Swaroop Ghosh,
Sujit Dey,
Anand Raghunathan,
Kaushik Roy:
Coping with Variations through System-Level Design.
VLSI Design 2009: 581-586 |
| 2008 |
|---|
| 154 | EE | Janar Thoguluva,
Anand Raghunathan,
Srimat T. Chakradhar:
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor.
DATE 2008: 1148-1153 |
| 153 | EE | Najwa Aaraj,
Anand Raghunathan,
Niraj K. Jha:
Dynamic Binary Instrumentation-Based Framework for Malware Defense.
DIMVA 2008: 64-87 |
| 152 | EE | Najwa Aaraj,
Anand Raghunathan,
Niraj K. Jha:
Analysis and design of a hardware/software trusted platform module for embedded systems.
ACM Trans. Embedded Comput. Syst. 8(1): (2008) |
| 151 | EE | Krishna Sekar,
Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication.
IEEE Trans. VLSI Syst. 16(10): 1413-1426 (2008) |
| 150 | EE | Dimitris Gizopoulos,
Mihalis Psarakis,
Miltiadis Hatzimihail,
M. Maniatakos,
Antonis M. Paschalis,
Anand Raghunathan,
Srivaths Ravi:
Systematic Software-Based Self-Test for Pipelined Processors.
IEEE Trans. VLSI Syst. 16(11): 1441-1453 (2008) |
| 2007 |
|---|
| 149 | | Diana Marculescu,
Anand Raghunathan,
Ali Keshavarzi,
Vijaykrishnan Narayanan:
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007
ACM 2007 |
| 148 | EE | Saumya Chandra,
Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
System-on-Chip Power Management Considering Leakage Power Variations.
DAC 2007: 877-882 |
| 147 | EE | Mohammad Ali Ghodrat,
Kanishka Lahiri,
Anand Raghunathan:
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation.
DAC 2007: 883-886 |
| 146 | EE | Najwa Aaraj,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Energy and execution time analysis of a software-based trusted platform module.
DATE 2007: 1128-1133 |
| 145 | EE | Nikhil Bansal,
Kanishka Lahiri,
Anand Raghunathan:
Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis.
VLSI Design 2007: 513-520 |
| 144 | EE | Yunsi Fei,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Energy-optimizing source code transformations for operating system-driven embedded software.
ACM Trans. Embedded Comput. Syst. 7(1): (2007) |
| 143 | EE | Joel Coburn,
Srivaths Ravi,
Anand Raghunathan:
Hardware Accelerated Power Estimation
CoRR abs/0710.4742: (2007) |
| 142 | EE | Patrick Schaumont,
Anand Raghunathan:
Guest Editors' Introduction: Security and Trust in Embedded-Systems Design.
IEEE Design & Test of Computers 24(6): 518-520 (2007) |
| 141 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis.
IEEE Trans. VLSI Syst. 15(11): 1191-1204 (2007) |
| 140 | EE | Najwa Aaraj,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems.
IEEE Trans. VLSI Syst. 15(3): 296-308 (2007) |
| 139 | EE | Nachiketh R. Potlapally,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha,
Ruby B. Lee:
Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis.
IEEE Trans. VLSI Syst. 15(4): 465-470 (2007) |
| 138 | EE | Divya Arora,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Architectural Support for Run-Time Validation of Program Data Properties.
IEEE Trans. VLSI Syst. 15(5): 546-559 (2007) |
| 137 | EE | Nachiketh R. Potlapally,
Srivaths Ravi,
Anand Raghunathan,
Ruby B. Lee,
Niraj K. Jha:
Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution.
IEEE Trans. VLSI Syst. 15(5): 605-609 (2007) |
| 136 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Murugan Sankaradass,
Niraj K. Jha,
Srimat T. Chakradhar:
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.
IEEE Trans. VLSI Syst. 15(6): 699-710 (2007) |
| 135 | EE | Anish Muttreja,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Hybrid Simulation for Energy Estimation of Embedded Software.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1843-1854 (2007) |
| 134 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2035-2045 (2007) |
| 133 | EE | Anish Muttreja,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Automated Energy/Performance Macromodeling of Embedded Software.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 542-552 (2007) |
| 2006 |
|---|
| 132 | | Wolfgang Nebel,
Mircea R. Stan,
Anand Raghunathan,
Jörg Henkel,
Diana Marculescu:
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006
ACM 2006 |
| 131 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Architectural support for safe software execution on embedded processors.
CODES+ISSS 2006: 106-111 |
| 130 | EE | Mihalis Psarakis,
Dimitris Gizopoulos,
Miltiadis Hatzimihail,
Antonis M. Paschalis,
Anand Raghunathan,
Srivaths Ravi:
Systematic software-based self-test for pipelined processors.
DAC 2006: 393-398 |
| 129 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Murugan Sankaradass,
Niraj K. Jha,
Srimat T. Chakradhar:
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.
DAC 2006: 496-501 |
| 128 | EE | Phillip Stanley-Marbell,
Kanishka Lahiri,
Anand Raghunathan:
Adaptive data placement in an embedded multiprocessor thread library.
DATE 2006: 698-699 |
| 127 | EE | Krishna Sekar,
Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms.
DATE 2006: 728-733 |
| 126 | EE | Najwa Aaraj,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Architectures for efficient face authentication in embedded systems.
DATE Designers' Forum 2006: 1-6 |
| 125 | EE | Nachiketh R. Potlapally,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha,
Ruby B. Lee:
Satisfiability-based framework for enabling side-channel attacks on cryptographic software.
DATE Designers' Forum 2006: 18-23 |
| 124 | EE | Anish Muttreja,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Active Learning Driven Data Acquisition for Sensor Networks.
ISCC 2006: 929-934 |
| 123 | EE | Saumya Chandra,
Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Considering process variations during system-level power analysis.
ISLPED 2006: 342-345 |
| 122 | EE | Nachiketh R. Potlapally,
Srivaths Ravi,
Anand Raghunathan,
Ruby B. Lee,
Niraj K. Jha:
Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.
VLSI Design 2006: 299-304 |
| 121 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.
VLSI Design 2006: 473-476 |
| 120 | EE | Nachiketh R. Potlapally,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols.
IEEE Trans. Mob. Comput. 5(2): 128-143 (2006) |
| 119 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
A Scalable Synthesis Methodology for Application-Specific Processors.
IEEE Trans. VLSI Syst. 14(11): 1175-1188 (2006) |
| 118 | EE | Divya Arora,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors.
IEEE Trans. VLSI Syst. 14(12): 1295-1308 (2006) |
| 117 | EE | Kanishka Lahiri,
Anand Raghunathan,
Ganesh Lakshminarayana:
The LOTTERYBUS on-chip communication architecture.
IEEE Trans. VLSI Syst. 14(6): 596-608 (2006) |
| 116 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Use of Computation-Unit Integrated Memories in High-Level Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 1969-1989 (2006) |
| 115 | EE | Lin Zhong,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
RTL-Aware Cycle-Accurate Functional Power Estimation.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2103-2117 (2006) |
| 114 | EE | Loganathan Lingappan,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha,
Srimat T. Chakradhar:
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2193-2206 (2006) |
| 113 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Application-specific heterogeneous multiprocessor synthesis using extensible processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1589-1602 (2006) |
| 2005 |
|---|
| 112 | EE | Joel Coburn,
Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
SECA: security-enhanced communication architecture.
CASES 2005: 78-89 |
| 111 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Enhancing security through hardware-assisted run-time validation of program data properties.
CODES+ISSS 2005: 190-195 |
| 110 | EE | Anish Muttreja,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Hybrid simulation for embedded software energy estimation.
DAC 2005: 23-26 |
| 109 | EE | Pallav Gupta,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Efficient fingerprint-based user authentication for embedded systems.
DAC 2005: 244-247 |
| 108 | EE | Krishna Sekar,
Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology.
DAC 2005: 571-574 |
| 107 | EE | Joel Coburn,
Srivaths Ravi,
Anand Raghunathan:
Power emulation: a new paradigm for power estimation.
DAC 2005: 700-705 |
| 106 | EE | Divya Arora,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring.
DATE 2005: 178-183 |
| 105 | EE | Joel Coburn,
Srivaths Ravi,
Anand Raghunathan:
Hardware Accelerated Power Estimation.
DATE 2005: 528-529 |
| 104 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.
VLSI Design 2005: 551-556 |
| 103 | EE | Nikhil Bansal,
Kanishka Lahiri,
Anand Raghunathan,
Srimat T. Chakradhar:
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models.
VLSI Design 2005: 579-585 |
| 102 | EE | Loganathan Lingappan,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha,
Srimat T. Chakradhar:
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip.
VLSI Design 2005: 65-70 |
| 101 | EE | Tat Kee Tan,
Anand Raghunathan,
Niraj K. Jha:
Energy macromodeling of embedded operating systems.
ACM Trans. Embedded Comput. Syst. 4(1): 231-254 (2005) |
| 100 | EE | Weidong Wang,
Anand Raghunathan,
Ganesh Lakshminarayana,
Niraj K. Jha:
Input space-adaptive optimization for embedded-software synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1677-1693 (2005) |
| 99 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Generation of distributed logic-memory architectures through high-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1694-1711 (2005) |
| 2004 |
|---|
| 98 | EE | Kanishka Lahiri,
Anand Raghunathan:
Power analysis of system-level on-chip communication architectures.
CODES+ISSS 2004: 236-241 |
| 97 | EE | Srivaths Ravi,
Paul C. Kocher,
Ruby B. Lee,
Gary McGraw,
Anand Raghunathan:
Security as a new dimension in embedded system design.
DAC 2004: 753-760 |
| 96 | EE | Anish Muttreja,
Anand Raghunathan,
Srivaths Ravi,
Niraj K. Jha:
Automated energy/performance macromodeling of embedded software.
DAC 2004: 99-102 |
| 95 | | Tat Kee Tan,
Anand Raghunathan,
Niraj K. Jha:
An Energy-Aware Synthesis Methodology for OS-Driven Multi-Process Embedded Software.
ESA/VLSI 2004: 601-605 |
| 94 | EE | Lin Zhong,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Power estimation for cycle-accurate functional descriptions of hardware.
ICCAD 2004: 668-675 |
| 93 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
High-level synthesis using computation-unit integrated memories.
ICCAD 2004: 783-790 |
| 92 | EE | Yunsi Fei,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Energy-Optimizing Source Code Transformations for OS-driven Embedded Software.
VLSI Design 2004: 261-266 |
| 91 | EE | Weidong Wang,
Anand Raghunathan,
Niraj K. Jha:
Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization.
VLSI Design 2004: 267- |
| 90 | EE | Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
Tamper Resistance Mechanisms for Secure, Embedded Systems.
VLSI Design 2004: 605- |
| 89 | EE | Srivaths Ravi,
Anand Raghunathan,
Paul C. Kocher,
Sunil Hattangady:
Security in embedded systems: Design challenges.
ACM Trans. Embedded Comput. Syst. 3(3): 461-491 (2004) |
| 88 | EE | Weidong Wang,
Anand Raghunathan,
Ganesh Lakshminarayana,
Niraj K. Jha:
Input space adaptive design: a high-level methodology for optimizing energy and performance.
IEEE Trans. VLSI Syst. 12(6): 590-602 (2004) |
| 87 | EE | Ganesh Lakshminarayana,
Anand Raghunathan,
Kamal S. Khouri,
Niraj K. Jha,
Sujit Dey:
Common-case computation: a high-level energy and performance optimization technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 33-49 (2004) |
| 86 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Custom-instruction synthesis for extensible-processor platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(2): 216-228 (2004) |
| 85 | EE | Kanishka Lahiri,
Anand Raghunathan,
Ganesh Lakshminarayana,
Sujit Dey:
Design of high-performance system-on-chips using communication architecture tuners.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 620-636 (2004) |
| 84 | EE | Yunsi Fei,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
A hybrid energy-estimation technique for extensible processors.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 652-664 (2004) |
| 83 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Efficient power profiling for battery-driven embedded system design.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 919-932 (2004) |
| 82 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Design space exploration for optimizing on-chip communication architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(6): 952-961 (2004) |
| 81 | EE | Weidong Wang,
Anand Raghunathan,
Niraj K. Jha,
Sujit Dey:
Resource budgeting for Multiprocess High-level synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1010-1019 (2004) |
| 2003 |
|---|
| 80 | EE | Weidong Wang,
Tat Kee Tan,
Jiong Luo,
Yunsi Fei,
Li Shang,
Keith S. Vallerio,
Lin Zhong,
Anand Raghunathan,
Niraj K. Jha:
A comprehensive high-level synthesis system for control-flow intensive behaviors.
ACM Great Lakes Symposium on VLSI 2003: 11-14 |
| 79 | EE | Li Chen,
Srivaths Ravi,
Anand Raghunathan,
Sujit Dey:
A scalable software-based self-test methodology for programmable processors.
DAC 2003: 548-553 |
| 78 | EE | Anand Raghunathan,
Srivaths Ravi,
Sunil Hattangady,
Jean-Jacques Quisquater:
Securing Mobile Appliances: New Challenges for the System Designer.
DATE 2003: 10176-10183 |
| 77 | EE | Yunsi Fei,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Energy Estimation for Extensible Processors.
DATE 2003: 10682-10687 |
| 76 | EE | Davide Bertozzi,
Anand Raghunathan,
Luca Benini,
Srivaths Ravi:
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems.
DATE 2003: 10706-10713 |
| 75 | EE | Tat Kee Tan,
Anand Raghunathan,
Niraj K. Jha:
Software Architectural Transformations: A New Approach to Low Energy Embedded Software.
DATE 2003: 11046-11051 |
| 74 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
A Scalable Application-Specific Processor Synthesis Methodology.
ICCAD 2003: 283-290 |
| 73 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.
ICCAD 2003: 46-53 |
| 72 | EE | Nachiketh R. Potlapally,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Analyzing the energy consumption of security protocols.
ISLPED 2003: 30-35 |
| 71 | EE | Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
Embedding Security in Wireless Embedded Systems.
VLSI Design 2003: 269-270 |
| 70 | EE | Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
Efficient RTL Power Estimation for Large Designs.
VLSI Design 2003: 431-439 |
| 69 | EE | Weidong Wang,
Niraj K. Jha,
Anand Raghunathan,
Sujit Dey:
High-level Synthesis of Multi-process Behavioral Descriptions.
VLSI Design 2003: 467-473 |
| 68 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha:
High-level macro-modeling and estimation techniques for switching activity and power consumption.
IEEE Trans. VLSI Syst. 11(4): 538-557 (2003) |
| 67 | EE | Robert P. Dick,
Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha:
Analysis of power dissipation in embedded systems using real-time operating systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 615-627 (2003) |
| 66 | EE | Tat Kee Tan,
Anand Raghunathan,
Niraj K. Jha:
A simulation framework for energy-consumption analysis of OS-driven embedded applications.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1284-1294 (2003) |
| 2002 |
|---|
| 65 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Fast system-level power profiling for battery-efficient system design.
CODES 2002: 157-162 |
| 64 | EE | Kanishka Lahiri,
Sujit Dey,
Anand Raghunathan:
Communication architecture based power management for battery efficient system design.
DAC 2002: 691-696 |
| 63 | EE | Srivaths Ravi,
Anand Raghunathan,
Nachiketh R. Potlapally,
Murugan Sankaradass:
System design methodologies for a wireless security processing platform.
DAC 2002: 777-782 |
| 62 | EE | Chao Huang,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
High-level synthesis of distributed logic-memory architectures.
ICCAD 2002: 564-571 |
| 61 | EE | Fei Sun,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha:
Synthesis of custom processors based on extensible platforms.
ICCAD 2002: 641-648 |
| 60 | EE | Tat Kee Tan,
Anand Raghunathan,
Niraj K. Jha:
Embedded Operating System Energy Analysis and Macro-Modeling.
ICCD 2002: 515-520 |
| 59 | EE | Anand Raghunathan,
Nachiketh R. Potlapally,
Srivaths Ravi:
Securing Wireless Data: System Architecture Challenges.
ISSS 2002: 195-200 |
| 58 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey,
Debashis Panigrahi:
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design.
VLSI Design 2002: 261-267 |
| 57 | EE | Vijay Raghunathan,
Anand Raghunathan,
Mani B. Srivastava,
Milos D. Ercegovac:
High-Level Synthesis with SIMD Units.
VLSI Design 2002: 407-413 |
| 56 | EE | Weidong Wang,
Anand Raghunathan,
Ganesh Lakshminarayana,
Niraj K. Jha:
Input Space Adaptive Embedded Software Synthesis.
VLSI Design 2002: 711-718 |
| 55 | EE | J. Borel,
Anand Raghunathan,
Jim Sproch,
Michael Howells,
Janusz Rajski:
Innovations in Test Automation.
VTS 2002: 43-46 |
| 54 | EE | Kanishka Lahiri,
Sujit Dey,
Anand Raghunathan:
Communication-Based Power Management.
IEEE Design & Test of Computers 19(4): 118-130 (2002) |
| 53 | EE | Marcello Lajolo,
Anand Raghunathan,
Sujit Dey,
Luciano Lavagno:
Cosimulation-based power estimation for system-on-chip design.
IEEE Trans. VLSI Syst. 10(3): 253-266 (2002) |
| 52 | EE | Tat Kee Tan,
Anand Raghunathan,
Ganesh Lakshminarayana,
Niraj K. Jha:
High-level energy macromodeling of embedded software.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1037-1050 (2002) |
| 2001 |
|---|
| 51 | EE | Kanishka Lahiri,
Anand Raghunathan,
Ganesh Lakshminarayana:
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs.
DAC 2001: 15-20 |
| 50 | EE | Tat Kee Tan,
Anand Raghunathan,
Ganesh Lakshminarayana,
Niraj K. Jha:
High-level Software Energy Macro-modeling.
DAC 2001: 605-610 |
| 49 | EE | Weidong Wang,
Anand Raghunathan,
Ganesh Lakshminarayana,
Niraj K. Jha:
Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization.
DAC 2001: 738-743 |
| 48 | EE | Vijay Raghunathan,
Srivaths Ravi,
Anand Raghunathan,
Ganesh Lakshminarayana:
Transient Power Management Through High Level Synthesis.
ICCAD 2001: 545-552 |
| 47 | EE | Nachiketh R. Potlapally,
Michael S. Hsiao,
Anand Raghunathan,
Ganesh Lakshminarayana,
Srimat T. Chakradhar:
Accurate Power Macro-modeling Techniques for Complex RTL Circuits.
VLSI Design 2001: 235-241 |
| 46 | EE | Kanishka Lahiri,
Sujit Dey,
Anand Raghunathan:
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures.
VLSI Design 2001: 29-35 |
| 45 | EE | Debashis Panigrahi,
Sujit Dey,
Ramesh R. Rao,
Kanishka Lahiri,
Carla-Fabiana Chiasserini,
Anand Raghunathan:
Battery Life Estimation of Mobile Embedded Systems.
VLSI Design 2001: 57-63 |
| 44 | | Anand Raghunathan,
Sujit Dey:
Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies.
VLSI Design 2001: 9-10 |
| 43 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
System-level performance analysis for designing on-chipcommunication architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 768-783 (2001) |
| 2000 |
|---|
| 42 | EE | Robert P. Dick,
Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha:
Power analysis of embedded operating systems.
DAC 2000: 312-315 |
| 41 | EE | Kanishka Lahiri,
Anand Raghunathan,
Ganesh Lakshminarayana,
Sujit Dey:
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips.
DAC 2000: 513-518 |
| 40 | EE | Marcello Lajolo,
Anand Raghunathan,
Sujit Dey,
Luciano Lavagno:
Efficient Power Co-Estimation Techniques for System-on-Chip Design.
DATE 2000: 27-34 |
| 39 | | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Efficient Exploration of the SoC Communication Architecture Design Space.
ICCAD 2000: 424-430 |
| 38 | EE | Kanishka Lahiri,
Sujit Dey,
Anand Raghunathan:
Performance Analysis of Systems with Multi-Channel Communication Architectures.
VLSI Design 2000: 530-537 |
| 37 | EE | Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha:
Behavioral Synthesis of Fault Secure Controller/Datapaths Based on Aliasing Probability Analysis.
IEEE Trans. Computers 49(9): 865-885 (2000) |
| 36 | EE | Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha:
Incorporating speculative execution into scheduling ofcontrol-flow-intensive designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 308-324 (2000) |
| 1999 |
|---|
| 35 | EE | Ganesh Lakshminarayana,
Anand Raghunathan,
Kamal S. Khouri,
Niraj K. Jha,
Sujit Dey:
Common-Case Computation: A High-Level Technique for Power and Performance Optimization.
DAC 1999: 56-61 |
| 34 | EE | Kanishka Lahiri,
Anand Raghunathan,
Sujit Dey:
Fast performance analysis of bus-based system-on-chip communication architectures.
ICCAD 1999: 566-573 |
| 33 | EE | Pranav Ashar,
Anand Raghunathan,
Aarti Gupta,
Subhrajit Bhattacharya:
Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation.
ICCD 1999: 458-466 |
| 32 | | Kaushik Roy,
Anand Raghunathan,
Sujit Dey:
Low Power Design Methodologies for Systems-on-Chips.
VLSI Design 1999: 609 |
| 31 | EE | Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha,
Sujit Dey:
Power management in high-level synthesis.
IEEE Trans. VLSI Syst. 7(1): 7-15 (1999) |
| 30 | EE | Sujit Dey,
Anand Raghunathan,
Niraj K. Jha,
Kazutoshi Wakabayashi:
Controller-based power management for control-flow intensive designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1496-1508 (1999) |
| 29 | EE | Indradeep Ghosh,
Anand Raghunathan,
Niraj K. Jha:
Hierarchical test generation and design for testability methods for ASPPs and ASIPs.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 357-370 (1999) |
| 28 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha:
Register transfer level power optimization with emphasis on glitch analysis and reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(8): 1114-1131 (1999) |
| 1998 |
|---|
| 27 | | Sujit Dey,
Anand Raghunathan,
Rabindra K. Roy:
Considering Testability during High-level Design (Embedded Tutorial).
ASP-DAC 1998: 205-210 |
| 26 | EE | Marcello Lajolo,
Anand Raghunathan,
Sujit Dey,
Luciano Lavagno,
Alberto L. Sangiovanni-Vincentelli:
A case study on modeling shared memory access effects during performance analysis of HW/SW systems.
CODES 1998: 117-121 |
| 25 | EE | Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha:
Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions.
DAC 1998: 108-113 |
| 24 | EE | Pranav Ashar,
Subhrajit Bhattacharya,
Anand Raghunathan,
Akira Mukaiyama:
Verification of RTL generated from scheduled behavior in a high-level synthesis flow.
ICCAD 1998: 517-524 |
| 23 | EE | Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha,
Sujit Dey:
Transforming control-flow intensive designs to facilitate power management.
ICCAD 1998: 657-664 |
| 22 | | Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha,
Sujit Dey:
A Power Management Methodology for High-Level Synthesis.
VLSI Design 1998: 24-19 |
| 21 | EE | Indradeep Ghosh,
Anand Raghunathan,
Niraj K. Jha:
A design-for-testability technique for register-transfer level circuits using control/data flow extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 706-723 (1998) |
| 20 | EE | Sujit Dey,
Anand Raghunathan,
Kenneth D. Wagner:
Design for Testability Techniques at the Behavioral and Register-Transfer Levels.
J. Electronic Testing 13(2): 79-91 (1998) |
| 1997 |
|---|
| 19 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha,
Kazutoshi Wakabayashi:
Power Management Techniques for Control-Flow Intensive Designs.
DAC 1997: 429-434 |
| 18 | EE | Indradeep Ghosh,
Anand Raghunathan,
Niraj K. Jha:
Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs.
DAC 1997: 534-539 |
| 17 | EE | Srimat T. Chakradhar,
Anand Raghunathan:
Bottleneck removal algorithm for dynamic compaction in sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1157-1172 (1997) |
| 16 | EE | Anand Raghunathan,
Niraj K. Jha:
SCALP: an iterative-improvement-based low-power data path synthesis system.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1260-1277 (1997) |
| 15 | EE | Indradeep Ghosh,
Anand Raghunathan,
Niraj K. Jha:
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1001-1014 (1997) |
| 1996 |
|---|
| 14 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha:
Glitch Analysis and Reduction in Register Transfer Level.
DAC 1996: 331-336 |
| 13 | | Ganesh Lakshminarayana,
Anand Raghunathan,
Niraj K. Jha:
Behavioral Synthesis of Fault Secure Controller?Datapaths using Aliasing Probability Analysis.
FTCS 1996: 336-345 |
| 12 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha:
Register-transfer level estimation techniques for switching activity and power consumption.
ICCAD 1996: 158-165 |
| 11 | EE | Indradeep Ghosh,
Anand Raghunathan,
Niraj K. Jha:
A design for testability technique for RTL circuits using control/data flow extraction.
ICCAD 1996: 329-336 |
| 10 | EE | Anand Raghunathan,
Sujit Dey,
Niraj K. Jha,
Kazutoshi Wakabayashi:
Controller re-specification to minimize switching activity in controller/data path circuits.
ISLPED 1996: 301-304 |
| 9 | EE | Anand Raghunathan,
Srimat T. Chakradhar:
Dynamic test Sequence compaction for Sequential Circuits.
VLSI Design 1996: 170-173 |
| 1995 |
|---|
| 8 | EE | Srimat T. Chakradhar,
Anand Raghunathan:
Bottleneck removal algorithm for dynamic compaction and test cycles reduction.
EURO-DAC 1995: 98-104 |
| 7 | EE | Anand Raghunathan,
Srimat T. Chakradhar:
Acceleration techniques for dynamic vector compaction.
ICCAD 1995: 310-317 |
| 6 | EE | Anand Raghunathan,
Niraj K. Jha:
An iterative improvement algorithm for low power data path synthesis.
ICCAD 1995: 597-602 |
| 5 | EE | Indradeep Ghosh,
Anand Raghunathan,
Niraj K. Jha:
Design for hierarchical testability of RTL circuits obtained by behavioral synthesis.
ICCD 1995: 173-179 |
| 4 | | Anand Raghunathan,
Niraj K. Jha:
An ILP Formulation for Low Power Based on Minimizing Switched Capacitance During Data Path Allocation.
ISCAS 1995: 1069-1073 |
| 3 | EE | Anand Raghunathan,
Pranav Ashar,
Sharad Malik:
Test generation for cyclic combinational circuits.
VLSI Design 1995: 104-109 |
| 2 | EE | Anand Raghunathan,
Pranav Ashar,
Sharad Malik:
Test generation for cyclic combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1408-1414 (1995) |
| 1994 |
|---|
| 1 | | Anand Raghunathan,
Niraj K. Jha:
Behavioral Synthesis for low Power.
ICCD 1994: 318-322 |
