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| 2006 | ||
|---|---|---|
| 2 | EE | Pallav Gupta, Abhinav Agrawal, Niraj K. Jha: An Algorithm for Synthesis of Reversible Logic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2317-2330 (2006) |
| 2004 | ||
| 1 | EE | Abhinav Agrawal, Niraj K. Jha: Synthesis of Reversible Logic. DATE 2004: 1384-1385 |
| 1 | Pallav Gupta | [2] |
| 2 | Niraj K. Jha | [1] [2] |