| 2008 |
|---|
| 11 | EE | Jacob R. Minz,
Xin Zhao,
Sung Kyu Lim:
Buffered clock tree synthesis for 3D ICs under thermal variations.
ASP-DAC 2008: 504-509 |
| 2007 |
|---|
| 10 | EE | Eric Wong,
Jacob R. Minz,
Sung Kyu Lim:
Decoupling-Capacitor Planning and Sizing for Noise and Leakage Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2023-2034 (2007) |
| 2006 |
|---|
| 9 | EE | Jacob R. Minz,
Somaskanda Thyagaraja,
Sung Kyu Lim:
Optical routing for 3D system-on-package.
DATE 2006: 337-338 |
| 8 | EE | Eric Wong,
Jacob R. Minz,
Sung Kyu Lim:
Decoupling capacitor planning and sizing for noise and leakage reduction.
ICCAD 2006: 395-400 |
| 7 | EE | Eric Wong,
Jacob R. Minz,
Sung Kyu Lim:
Multi-Objective Module Placement For 3-D System-On-Package.
IEEE Trans. VLSI Syst. 14(5): 553-557 (2006) |
| 6 | EE | Jacob R. Minz,
Sung Kyu Lim:
Block-level 3-D Global Routing With an Application to 3-D Packaging.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2248-2257 (2006) |
| 5 | EE | Mongkol Ekpanyapong,
Jacob R. Minz,
Thaisiri Watewai,
Hsien-Hsin S. Lee,
Sung Kyu Lim:
Profile-guided microarchitectural floor planning for deep submicron processor design.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1289-1300 (2006) |
| 2005 |
|---|
| 4 | EE | Jacob R. Minz,
Sung Kyu Lim,
Cheng-Kok Koh:
3D module placement for congestion and power noise reduction.
ACM Great Lakes Symposium on VLSI 2005: 458-461 |
| 2004 |
|---|
| 3 | EE | Jacob R. Minz,
Sung Kyu Lim:
Layer assignment for reliable system-on-package.
ASP-DAC 2004: 31-37 |
| 2 | EE | Mongkol Ekpanyapong,
Jacob R. Minz,
Thaisiri Watewai,
Hsien-Hsin S. Lee,
Sung Kyu Lim:
Profile-guided microarchitectural floorplanning for deep submicron processor design.
DAC 2004: 634-639 |
| 1 | EE | Jacob R. Minz,
Mohit Pathak,
Sung Kyu Lim:
Net and Pin Distribution for 3D Package Global Routing.
DATE 2004: 1410-1411 |
