Tomohiro Yoneda

2008
41	EE	Chammika Mannakkara, Tomohiro Yoneda: Asynchronous pipeline controller based on early acknowledgement protocol. ACSD 2008: 118-127
40	EE	Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ACSD 2008: 50-55
39	EE	Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: Hazard Checking of Timed Asynchronous Circuits Revisited. Fundam. Inform. 88(4): 411-435 (2008)
38	EE	David Walter, Scott Little, Chris J. Myers, Nicholas Seegmiller, Tomohiro Yoneda: Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2223-2235 (2008)
37	EE	Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: A Conservative Framework for Safety-Failure Checking. IEICE Transactions 91-D(3): 642-654 (2008)
2007
36		Kedar S. Namjoshi, Tomohiro Yoneda, Teruo Higashino, Yoshio Okamura: Automated Technology for Verification and Analysis, 5th International Symposium, ATVA 2007, Tokyo, Japan, October 22-25, 2007, Proceedings Springer 2007
35	EE	Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: Hazard Checking of Timed Asynchronous Circuits Revisited. ACSD 2007: 51-60
34	EE	David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda: Symbolic Model Checking of Analog/Mixed-Signal Circuits. ASP-DAC 2007: 316-323
33	EE	Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda: Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 592-605 (2007)
32	EE	Tomohiro Yoneda, Chris J. Myers: Synthesis of Timed Circuits Based on Decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1177-1195 (2007)
31	EE	Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. IEICE Transactions 90-A(12): 2790-2799 (2007)
2006
30	EE	Tomohiro Yoneda, Chris J. Myers: Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. ATVA 2006: 229-244
29	EE	Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. CIT 2006: 172
28	EE	Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda: Verification of analog/mixed-signal circuits using labeled hybrid petri nets. ICCAD 2006: 275-282
27	EE	Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of timed circuits with failure-directed abstractions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 403-412 (2006)
2005
26	EE	Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers: High Level Synthesis of Timed Asynchronous Circuits. ASYNC 2005: 178-189
25	EE	Tomoya Kitai, Tomohiro Yoneda, Chris J. Myers: Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation. IEICE Transactions 88-D(11): 2555-2564 (2005)
24	EE	Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers: Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. IEICE Transactions 88-D(7): 1646-1661 (2005)
2004
23	EE	Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers: Synthesis of Speed Independent Circuits Based on Decomposition. ASYNC 2004: 135-145
22	EE	Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers: Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. ATVA 2004: 339-353
21	EE	Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda: Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. ATVA 2004: 426-440
2003
20	EE	Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda: Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. ICCAD 2003: 424-432
19	EE	Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of Timed Circuits with Failure Directed Abstractions. ICCD 2003: 28-35
2002
18	EE	Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers: Automatic Derivation of Timing Constraints by Failure Analysis. CAV 2002: 195-208
17	EE	Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers: Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC 2002: 210-220
16	EE	Eric Mercer, Chris J. Myers, Tomohiro Yoneda: Modular Synthesis of Timed Circuits using Partial Order Reduction. Electr. Notes Theor. Comput. Sci. 65(6): (2002)
2001
15	EE	Bin Zhou, Tomohiro Yoneda, Bernd-Holger Schlingloff: Conformance and mirroring for timed asychronous circuits. ASP-DAC 2001: 341-346
14	EE	Bin Zhou, Tomohiro Yoneda, Chris J. Myers: Framework of Timed Trace Theoretic Verification Revisited. Asian Test Symposium 2001: 437-442
13	EE	Tomoya Kitai, Tomohiro Yoneda: Partial Order Reduction in Verification of Wheel Structured Parameterized Circuits. PRDC 2001: 173-182
12	EE	Hiroshi Toshima, Tomohiro Yoneda: Efficient verification by exploiting symmetry and abstraction. Systems and Computers in Japan 32(14): 41-53 (2001)
11	EE	Koichi Masukura, Minoru Tomisaka, Tomohiro Yoneda: Verification of asynchronous circuits based on zero-suppressed BDDs. Systems and Computers in Japan 32(2): 43-54 (2001)
2000
10		Tomohiro Yoneda: VINAS-P: A Tool for Trace Theoretic Verification of Timed Asynchronous Circuits. CAV 2000: 572-575
1999
9	EE	Tomohiro Yoneda, Hiroshi Ryu: Timed Trace Theoretic Verification Using Partial Order Reduction. ASYNC 1999: 108-
8	EE	Märt Saarepera, Tomohiro Yoneda: A Self-Timed Implementation of Boolean Functions. ASYNC 1999: 243-
7		Tomohiro Yoneda: Verification of Abstracted Instruction Cache of TITAC2: A Case Study. VLSI 1999: 373-384
1998
6	EE	Tomohiro Yoneda, Yutaka Ohtsuka, Märt Saarepera: Verification of Parameterized Asynchronous Circuits: A Case Study. ACSD 1998: 64-74
5	EE	Tomohiro Yoneda, Bin Zhou, Bernd-Holger Schlingloff: Verification of Bounded Delay Asynchronous Circuits with Timed Traces. AMAST 1998: 59-73
1997
4		Tomohiro Yoneda, Bernd-Holger Schlingloff: Efficient Verification of Parallel Real-Time Systems. Formal Methods in System Design 11(2): 187-215 (1997)
3	EE	Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya: Verification of asynchronous logic circuit design using process algebra. Systems and Computers in Japan 28(8-9): 33-43 (1997)
1996
2		Tomohiro Yoneda, Hideyuki Hatori, Atsushi Takahara, Shin-ichi Minato: BDDs vs. Zero-Suppressed BDDs: for CTL Symbolic Model Checking of Petri Nets. FMCAD 1996: 435-449
1993
1		Tomohiro Yoneda, Atsufumi Shibayama, Bernd-Holger Schlingloff, Edmund M. Clarke: Efficient Verification of Parallel Real-Time Systems. CAV 1993: 321-346

Coauthor Index

1	Frédéric Béal	[35] [37] [39]
2	Edmund M. Clarke	[1]
3	Naohiro Hamada	[31] [40]
4	Hideyuki Hatori	[2]
5	Teruo Higashino	[36]
6	Nattha Jindapetch	[29] [31]
7	Manabu Kato	[26]
8	Tomoya Kitai	[13] [17] [18] [25]
9	Scott Little	[19] [21] [27] [28] [34] [38]
10	Chammika Mannakkara	[41]
11	Koichi Masukura	[11]
12	Atsushi Matsumoto	[26]
13	Eric Mercer (Eric G. Mercer)	[16] [17]
14	Shin-ichi Minato	[2]
15	Chris J. Myers	[14] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33] [34] [35] [37] [38] [39] [40]
16	Kedar S. Namjoshi	[36]
17	Takashi Nanya	[3] [29] [31] [40]
18	Curtis A. Nelson	[20] [33]
19	Yusuke Oguro	[17]
20	Yutaka Ohtsuka	[6]
21	Yoshio Okamura	[36]
22	Hiroomi Onda	[23]
23	Denduang Pradubsuwun	[22] [24]
24	Hiroshi Ryu	[9]
25	Märt Saarepera	[6] [8]
26	Hiroshi Saito	[29] [31] [40]
27	Bernd-Holger Schlingloff	[1] [4] [5] [15]
28	Nicholas Seegmiller	[21] [28] [34] [38]
29	Atsufumi Shibayama	[1] [3]
30	Yuuki Shiga	[40]
31	Atsushi Takahara	[2]
32	Minoru Tomisaka	[11]
33	Hiroshi Toshima	[12]
34	David Walter	[19] [21] [27] [28] [34] [38]
35	Hao Zheng	[19] [27]
36	Bin Zhou	[5] [14] [15]

Colors in the list of coauthors