2009 |
25 | EE | Amirali Shayan Arani,
Xiang Hu,
He Peng,
Wenjian Yu,
Wanping Zhang,
Chung-Kuan Cheng,
Mikhail Popovich,
Xiaoming Chen,
Lew Chua-Eoan,
Xiaohua Kong:
Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network.
ISQED 2009: 576-581 |
24 | EE | Shan Zeng,
Wenjian Yu,
Wanping Zhang,
Jian Wang,
Xianlong Hong,
Chung-Kuan Cheng:
Efficient power network analysis with complete inductive modeling.
ISQED 2009: 770-775 |
2008 |
23 | EE | Jian Cui,
Gengsheng Chen,
Ruijing Shen,
Sheldon X.-D. Tan,
Wenjian Yu,
Jiarong Tong:
Variational capacitance modeling using orthogonal polynomial method.
ACM Great Lakes Symposium on VLSI 2008: 23-28 |
22 | EE | Fang Gong,
Wenjian Yu,
Zeyi Wang,
Zhiping Yu,
Changhao Yan:
Efficient techniques for 3-D impedance extraction using mixed boundary element method.
ASP-DAC 2008: 158-163 |
21 | EE | Ling Zhang,
Wenjian Yu,
Haikun Zhu,
Alina Deutsch,
George A. Katopis,
Daniel M. Dreps,
Ernest S. Kuh,
Chung-Kuan Cheng:
Low power passive equalizer optimization using tritonic step response.
DAC 2008: 570-573 |
20 | EE | Wanping Zhang,
Yi Zhu,
Wenjian Yu,
Ling Zhang,
Rui Shi,
He Peng,
Zhi Zhu,
Lew Chua-Eoan,
Rajeev Murgai,
Toshiyuki Shibuya,
Nuriyoki Ito,
Chung-Kuan Cheng:
Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network.
DATE 2008: 537-540 |
19 | EE | Wangyang Zhang,
Wenjian Yu,
Zeyi Wang,
Zhiping Yu,
Rong Jiang,
Jinjun Xiong:
An Efficient Method for Chip-Level Statistical Capacitance Extraction Considering Process Variations with Spatial Correlation.
DATE 2008: 580-585 |
18 | EE | Ling Zhang,
Wenjian Yu,
Yulei Zhang,
Renshen Wang,
Alina Deutsch,
George A. Katopis,
Daniel M. Dreps,
James F. Buckwalter,
Ernest S. Kuh,
Chung-Kuan Cheng:
Low Power Passive Equalizer Design for Computer Memory Links.
Hot Interconnects 2008: 51-56 |
17 | EE | Rui Shi,
Wenjian Yu,
Yi Zhu,
Chung-Kuan Cheng,
Ernest S. Kuh:
Efficient and accurate eye diagram prediction for high speed signaling.
ICCAD 2008: 655-661 |
16 | EE | Ling Zhang,
Wenjian Yu,
Haikun Zhu,
Wanping Zhang,
Chung-Kuan Cheng:
Clock Skew Analysis via Vector Fitting in Frequency Domain.
ISQED 2008: 476-479 |
15 | EE | Wenjian Yu,
Xiren Wang,
Zuochang Ye,
Zeyi Wang:
Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1508-1513 (2008) |
2007 |
14 | EE | Xiren Wang,
Wenjian Yu,
Zeyi Wang:
A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy Substrates.
ASP-DAC 2007: 62-67 |
13 | EE | Zhuoyuan Li,
Xianlong Hong,
Qiang Zhou,
Shan Zeng,
Jinian Bian,
Wenjian Yu,
Hannah Honghua Yang,
Vijay Pitchumani,
Chung-Kuan Cheng:
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 645-658 (2007) |
2006 |
12 | EE | Mengsheng Zhang,
Wenjian Yu,
Yu Du,
Zeyi Wang:
An efficient algorithm for 3-D reluctance extraction considering high frequency effect.
ASP-DAC 2006: 521-526 |
11 | EE | Xiren Wang,
Wenjian Yu,
Zeyi Wang:
A new boundary element method for accurate modeling of lossy substrates with arbitrary doping profiles.
ASP-DAC 2006: 683-688 |
10 | EE | Changhao Yan,
Wenjian Yu,
Zeyi Wang:
Calculating frequency-dependent inductance of VLSI interconnect by complete multiple reciprocity boundary element method.
ASP-DAC 2006: 844-849 |
9 | EE | Changhao Yan,
Wenjian Yu,
Zeyi Wang:
A Mixed Boundary Element Method for Extracting Frequency- Inductances of 3D Interconnects.
ISQED 2006: 709-716 |
8 | EE | Wenjian Yu,
Mengsheng Zhang,
Zeyi Wang:
Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 12-18 (2006) |
7 | EE | Xiren Wang,
Wenjian Yu,
Zeyi Wang:
Efficient Direct Boundary Element Method for Resistance Extraction of Substrate With Arbitrary Doping Profile.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 3035-3042 (2006) |
2005 |
6 | EE | Xiren Wang,
Wenjian Yu,
Zeyi Wang,
Xianlong Hong:
An improved direct boundary element method for substrate coupling resistance extraction.
ACM Great Lakes Symposium on VLSI 2005: 84-87 |
5 | EE | Xiren Wang,
Wenjian Yu,
Zeyi Wang:
Substrate resistance extraction with direct boundary element method.
ASP-DAC 2005: 208-211 |
4 | EE | Xiren Wang,
Deyan Liu,
Wenjian Yu,
Zeyi Wang:
Improved Boundary Element Method for Fast 3-D Interconnect Resistance Extraction.
IEICE Transactions 88-C(2): 232-240 (2005) |
2004 |
3 | EE | Xiren Wang,
Deyan Liu,
Wenjian Yu,
Zeyi Wang:
Fast and accurate extraction of 3-D interconnect resistance: improved quasi-multiple medium accelerated BEM method.
ASP-DAC 2004: 707-709 |
2003 |
2 | EE | Wenjian Yu,
Zeyi Wang,
Xianlong Hong:
Enhanced QMM-BEM Solver for 3-D Finite-Domain Capacitance Extraction with Multilayered Dielectrics.
ICCD 2003: 58-63 |
2001 |
1 | EE | Wenjian Yu,
Zeyi Wang:
An efficient quasi-multiple medium algorithm fo the capacitance extraction of actual 3-D VLSI interconnects.
ASP-DAC 2001: 366-372 |