Zaid Al-Ars

2008
33	EE	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis: Test Set Development for Cache Memory in Modern Microprocessors. IEEE Trans. VLSI Syst. 16(6): 725-732 (2008)
2007
32		Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev: Manifestation of Precharge Faults in High Speed DRAM Devices. DDECS 2007: 179-184
31	EE	Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero: PPM Reduction on Embedded Memories in System on Chip. European Test Symposium 2007: 85-90
30	EE	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev: Optimizing Test Length for Soft Faults in DRAM Devices. VTS 2007: 59-66
2006
29	EE	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: Space of DRAM fault models and corresponding testing. DATE 2006: 1252-1257
28	EE	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor: Opens and Delay Faults in CMOS RAM Address Decoders. IEEE Trans. Computers 55(12): 1630-1639 (2006)
27	EE	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Sultan M. Al-Harbi: Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2989-2996 (2006)
2005
26	EE	Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath: Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. Asian Test Symposium 2005: 434-439
25	EE	Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor: Framework for Fault Analysis and Test Generation in DRAMs. DATE 2005: 1020-1021
2004
24	EE	Said Hamdioui, John Delos Reyes, Zaid Al-Ars: Evaluation of Intra-Word Faults in Word-Oriented RAMs. Asian Test Symposium 2004: 283-288
23	EE	Zaid Al-Ars, A. J. van de Goor: Soft Faults and the Importance of Stresses in Memory Testing. DATE 2004: 1084-1091
22	EE	A. J. van de Goor, Said Hamdioui, Zaid Al-Ars: The Effectiveness of the Scan Test and Its New Variants. MTDT 2004: 26-31
21	EE	Zaid Al-Ars, Martin Herzog, Ivo Schanstra, A. J. van de Goor: Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. MTDT 2004: 32-37
20	EE	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. VTS 2004: 117-122
19	EE	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 737-757 (2004)
2003
18	EE	Zaid Al-Ars, A. J. van de Goor: Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. Asian Test Symposium 2003: 24-27
17	EE	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: March SL: A Test For All Static Linked Memory Faults. Asian Test Symposium 2003: 372-377
16	EE	Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter: Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. DATE 2003: 10484-10489
15	EE	Zaid Al-Ars, A. J. van de Goor: Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. MTDT 2003: 27-32
14	EE	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: A Fault Primitive Based Analysis of Linked Faults in RAMs. MTDT 2003: 33-
13	EE	Zaid Al-Ars, A. J. van de Goor: Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs. IEEE Trans. Computers 52(3): 293-309 (2003)
12	EE	Zaid Al-Ars, A. J. van de Goor: Test generation and optimization for DRAM cell defects using electrical simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1371-1384 (2003)
11	EE	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. J. Electronic Testing 19(2): 195-205 (2003)
2002
10	EE	Zaid Al-Ars, A. J. van de Goor: DRAM Specific Approximation of the Faulty Behavior of Cell Defects. Asian Test Symposium 2002: 98-103
9	EE	Zaid Al-Ars, A. J. van de Goor: Modeling Techniques and Tests for Partial Faults in Memory Devices. DATE 2002: 89-93
8	EE	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor: Testing Static and Dynamic Faults in Random Access Memories. VTS 2002: 395-400
7	EE	Zaid Al-Ars, A. J. van de Goor: Approximating Infinite Dynamic Behavior for DRAM Cell Defects. VTS 2002: 401-406
2001
6	EE	Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter: A Memory Specific Notation for Fault Modeling. Asian Test Symposium 2001: 43-
5	EE	Zaid Al-Ars, A. J. van de Goor: Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. DATE 2001: 496-503
4		Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter: Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs. ITC 2001: 783-792
3	EE	Zaid Al-Ars, A. J. van de Goor: Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. MTDT 2001: 59-64
2000
2	EE	Zaid Al-Ars, A. J. van de Goor: Impact of memory cell array bridges on the faulty behavior in embedded DRAMs. Asian Test Symposium 2000: 282-289
1	EE	A. J. van de Goor, Zaid Al-Ars: Functional Memory Faults: A Formal Notation and a Taxonomy. VTS 2000: 281-290

Coauthor Index

1	Sultan M. Al-Harbi	[27]
2	Jens Braun	[4] [6] [16]
3	Jose Calero	[31]
4	Georgi Gaydadjiev (G. N. Gaydadjiev)	[30] [32] [33]
5	A. J. van de Goor	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [25] [27] [28] [29]
6	Said Hamdioui	[8] [11] [14] [17] [19] [20] [22] [24] [25] [26] [27] [28] [29] [30] [31] [32] [33]
7	Martin Herzog	[21]
8	Javier Jiménez	[31]
9	Georg Mueller	[25]
10	John Delos Reyes	[24]
11	Detlev Richter	[4] [6] [16]
12	Mike Rodgers	[11] [17] [19]
13	Ivo Schanstra	[21]
14	Stamatis Vassiliadis	[33]
15	Jörg E. Vollrath	[26]