Jerry R. Burch

2007
31	EE	Alfred Kölbl, Jerry R. Burch, Carl Pixley: Memory Modeling in ESL-RTL Equivalence Checking. DAC 2007: 205-209
30	EE	Roberto Passerone, Jerry R. Burch, Alberto L. Sangiovanni-Vincentelli: Refinement preserving approximations for the design and verification of heterogeneous systems. Formal Methods in System Design 31(1): 1-33 (2007)
2006
29	EE	Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske: Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 743-755 (2006)
28	EE	Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch: Linear cofactor relationships in Boolean functions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1011-1023 (2006)
2005
27	EE	Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch: Detecting support-reducing bound sets using two-cofactor symmetries. ASP-DAC 2005: 266-271
2004
26	EE	Roberto Passerone, Jerry R. Burch, Alberto L. Sangiovanni-Vincentelli: Conservative approximations for heterogeneous design. EMSOFT 2004: 155-164
2001
25	EE	Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli: Overcoming Heterophobia: Modeling Concurrency in Heterogeneous Systems. ACSD 2001: 13-
24	EE	Jerry R. Burch, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli: Using Multiple Levels of Abstractions in Embedded Software Design. EMSOFT 2001: 324-343
2000
23	EE	Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan: Sibling-substitution-based BDD minimization using don't cares. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 44-55 (2000)
1998
22	EE	Jerry R. Burch, Vigyan Singhal: Robust latch mapping for combinational equivalence checking. ICCAD 1998: 563-569
21	EE	Jerry R. Burch, Vigyan Singhal: Tight integration of combinational verification methods. ICCAD 1998: 570-576
20		Peter A. Beerel, Jerry R. Burch, Teresa H. Y. Meng: Checking Combinational Equivalence of Speed-Independent Circuits. Formal Methods in System Design 13(1): 37-85 (1998)
1997
19	EE	Youpyo Hong, Peter A. Beerel, Jerry R. Burch, Kenneth L. McMillan: Safe BDD Minimization Using Don't Cares. DAC 1997: 208-213
1996
18	EE	Jerry R. Burch: Techniques for Verifying Superscalar Microprocessors. DAC 1996: 552-557
17		Phillip J. Windley, Jerry R. Burch: Mechanically Checking a Lemma Used in an Automatic Verification Tool. FMCAD 1996: 362-376
1995
16	EE	Robert B. Jones, David L. Dill, Jerry R. Burch: Efficient validity checking for processor verification. ICCAD 1995: 2-6
1994
15		Jerry R. Burch, David L. Dill: Automatic verification of Pipelined Microprocessor Control. CAV 1994: 68-80
14	EE	Jerry R. Burch, Edmund M. Clarke, David E. Long, Kenneth L. McMillan, David L. Dill: Symbolic model checking for sequential circuit verification. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 401-424 (1994)
1993
13	EE	Peter A. Beerel, Jerry R. Burch, Teresa H. Y. Meng: Efficient verification of determinate speed-independent circuits. ICCAD 1993: 261-267
12	EE	Jerry R. Burch, David L. Dill, Elizabeth Wolf, Giovanni De Micheli: Modeling hierarchical combinational circuits. ICCAD 1993: 612-617
1992
11	EE	Jerry R. Burch, David E. Long: Efficient Boolean function matching. ICCAD 1992: 408-411
10		Jerry R. Burch: Delay Models for Verifying Speed-Dependent Asynchronous Circuits. ICCD 1992: 270-274
9		Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang: Symbolic Model Checking: 10^20 States and Beyond Inf. Comput. 98(2): 142-170 (1992)
1991
8	EE	Jerry R. Burch, Edmund M. Clarke, David E. Long: Representing Circuits More Efficiently in Symbolic Model Checking. DAC 1991: 403-407
7	EE	Jerry R. Burch: Using BDDs to Verify Multipliers. DAC 1991: 408-412
6		Jerry R. Burch, Edmund M. Clarke, David E. Long: Symbolic Model Checking with Partitioned Transistion Relations. VLSI 1991: 49-58
1990
5		Jerry R. Burch: Verifying Liveness Properties by Verifying Safety Properties. CAV 1990: 224-232
4	EE	Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill: Sequential Circuit Verification Using Symbolic Model Checking. DAC 1990: 46-51
3		Jerry R. Burch, Edmund M. Clarke, Kenneth L. McMillan, David L. Dill, L. J. Hwang: Symbolic Model Checking: 10^20 States and Beyond LICS 1990: 428-439
1989
2		Jerry R. Burch: Combining CTL, Trace Theory and Timing Models. Automatic Verification Methods for Finite State Systems 1989: 334-348
1985
1		Alain J. Martin, Jerry R. Burch: Fair Mutual Exclusion with Unfair P and V Operations. Inf. Process. Lett. 21(2): 97-100 (1985)

Coauthor Index

1	Peter A. Beerel	[13] [19] [20] [23]
2	Robert K. Brayton	[29]
3	Malgorzata Chrzanowska-Jeske	[27] [28] [29]
4	Edmund M. Clarke	[3] [4] [6] [8] [9] [14]
5	David L. Dill	[3] [4] [9] [12] [14] [15] [16]
6	Youpyo Hong	[19] [23]
7	L. J. Hwang	[3] [9]
8	Robert B. Jones	[16]
9	Alfred Kölbl	[31]
10	David E. Long	[6] [8] [11] [14]
11	Alain J. Martin	[1]
12	Kenneth L. McMillan	[3] [4] [9] [14] [19] [23]
13	Teresa H. Y. Meng	[13] [20]
14	Giovanni De Micheli	[12]
15	Alan Mishchenko	[27] [28] [29]
16	Roberto Passerone	[24] [25] [26] [30]
17	Carl Pixley	[31]
18	Alberto L. Sangiovanni-Vincentelli	[24] [25] [26] [30]
19	Vigyan Singhal	[21] [22]
20	Subarnarekha Sinha	[29]
21	Phillip J. Windley	[17]
22	Elizabeth Wolf	[12]
23	Jin S. Zhang	[27] [28] [29]

Colors in the list of coauthors