Jawahar Jain

2006
38	EE	Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, E. Allen Emerson: Under-approximation Heuristics for Grid-based Bounded Model Checking. Electr. Notes Theor. Comput. Sci. 135(2): 31-46 (2006)
37	EE	Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain: On partitioning and symbolic model checking. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 780-788 (2006)
2005
36	EE	Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill: A New Reachability Algorithm for Symmetric Multi-processor Architecture. ATVA 2005: 26-38
35	EE	Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu: Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes. Asian Test Symposium 2005: 460
34	EE	Subramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle: Error Detection Using BMC in a Parallel Environment. CHARME 2005: 354-358
33	EE	Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson: Predictive Reachability Using a Sample-Based Approach. CHARME 2005: 388-392
32	EE	Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson: Multi-threaded reachability. DAC 2005: 467-470
31	EE	Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain: On Partitioning and Symbolic Model Checking. FM 2005: 497-511
2004
30	EE	Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson: A Partitioning Methodology for BDD-Based Verification. FMCAD 2004: 399-413
29	EE	Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain: Can SAT be used to Improve Sequential ATPG Methods? VLSI Design 2004: 585-
2003
28	EE	Subramanian K. Iyer, Debashis Sahoo, Christian Stangier, Amit Narayan, Jawahar Jain: Improved Symbolic Verification Using Partitioning Techniques. CHARME 2003: 410-424
27	EE	Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain: Solving the latch mapping problem in an industrial setting. DAC 2003: 442-447
2002
26		Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain: Improving Sequential ATPG Using SAT Methods. IWLS 2002: 79-84
25		Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita: Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods in System Design 21(1): 95-101 (2002)
2001
24	EE	Jawahar Jain, Ingo Wegener, Masahiro Fujita: A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. IEEE Trans. Computers 50(11): 1289-1290 (2001)
2000
23	EE	Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita: Automatic partitioning for efficient combinatorial verification. ASP-DAC 2000: 67-72
22	EE	Jawahar Jain, K. Mohanram, Dinos Moundanos, Ingo Wegener, Yuan Lu: Analysis of composition complexity and how to obtain smaller canonical graphs. DAC 2000: 681-686
21	EE	Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita: Efficient variable ordering using aBDD based sampling. DAC 2000: 687-692
20	EE	Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita: Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design 2000: 436-441
19	EE	Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao: Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS 2000: 263-270
1999
18	EE	Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni: Multiple Error Diagnosis Based on Xlists. DAC 1999: 660-665
17	EE	Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: An Efficient Filter-Based Approach for Combinational Verification. DATE 1999: 132-137
16	EE	Rajeev Murgai, Jawahar Jain, Masahiro Fujita: Efficient Scheduling Techniques for ROBDD Construction. VLSI Design 1999: 394-401
15	EE	Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: An efficient filter-based approach for combinational verification. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1542-1557 (1999)
1998
14	EE	Jawahar Jain, William Adams, Masahiro Fujita: Sampling schemes for computing OBDD variable orderings. ICCAD 1998: 631-638
1997
13	EE	Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Reachability analysis using partitioned-ROBDDs. ICCAD 1997: 388-393
12		Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli: A Survey of Techniques for Formal Verification of Combinational Circuits. ICCD 1997: 445-454
11	EE	Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli: Formal Verification of Combinational Circuit. VLSI Design 1997: 218-225
10		Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell: Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. IEEE Trans. Computers 46(11): 1230-1245 (1997)
1996
9		Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita: Decomposition Techniques for Efficient ROBDD Construction. FMCAD 1996: 419-434
8	EE	Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli: Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. ICCAD 1996: 547-554
7	EE	Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: On More Efficient Combinational ATPG Using Functional Learning. VLSI Design 1996: 107-110
6	EE	Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: A study of composition schemes for mixed apply/compose based construction of ROBDDs. VLSI Design 1996: 249-253
1995
5	EE	Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita: Advanced Verification Techniques Based on Learning. DAC 1995: 420-426
4	EE	Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross: Efficient variable ordering and partial representation algorithm. VLSI Design 1995: 81-86
1994
3		James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell: Efficient Algorithmic Circuit Verification Using Indexed BDDs. FTCS 1994: 266-275
1992
2		Jawahar Jain, Jacob A. Abraham, James R. Bitner, Donald S. Fussell: Probabilistic Verification of Boolean Functions. Formal Methods in System Design 1(1): 61-115 (1992)
1991
1		Jawahar Jain, Jim Bitner, Donald S. Fussell, Jacob A. Abraham: Probabilistic Design Verification. ICCAD 1991: 468-471

Coauthor Index

1	Magdy S. Abadir	[3] [10]
2	Jacob A. Abraham	[1] [2] [3] [4] [7] [10] [15] [17] [25]
3	William Adams	[14]
4	James R. Bitner	[2] [3] [4] [10]
5	Jim Bitner	[1]
6	Pradeep Bollineni	[18]
7	Vamsi Boppana	[18] [19] [20]
8	Robert K. Brayton	[6] [9] [13]
9	Edmund M. Clarke	[21]
10	C. Coelho	[9]
11	David L. Dill	[30] [32] [33] [36]
12	E. Allen Emerson	[30] [31] [32] [33] [37] [38]
13	Masahiro Fujita	[5] [6] [7] [8] [9] [11] [12] [14] [15] [16] [17] [18] [19] [20] [21] [23] [24] [25]
14	Donald S. Fussell	[1] [2] [3] [4] [7] [10] [15] [17] [25]
15	Indradeep Ghosh	[20]
16	Michael S. Hsiao	[19] [26] [29]
17	Adrian J. Isles	[13]
18	Subramanian K. Iyer	[28] [30] [31] [32] [33] [34] [35] [36] [37] [38]
19	Ankur Jain	[19]
20	Sunil P. Khatri	[6] [9]
21	Yuan Lu	[21] [22]
22	K. Mohanram	[22]
23	Dinos Moundanos	[4] [22]
24	Rajarshi Mukherjee	[5] [7] [15] [17] [18] [19] [20] [23] [25] [27]
25	Rajeev Murgai	[16]
26	Amit Narayan	[6] [8] [9] [11] [12] [13] [28] [30]
27	Kelvin Ng	[27]
28	Mukul R. Prasad	[26] [27] [29] [34]
29	Don E. Ross	[4]
30	Debashis Sahoo	[28] [30] [31] [32] [33] [34] [35] [36] [37] [38]
31	Alberto L. Sangiovanni-Vincentelli	[6] [8] [9] [11] [12] [13]
32	Takeshi Shimizu	[35]
33	Thomas Sidle	[34]
34	Christian Stangier	[28] [30]
35	Koichiro Takayama	[15] [17] [23] [25]
36	Ingo Wegener	[22] [24]