| 2009 |
|---|
| 77 | EE | Liang Guang,
Ethiopia Nigussie,
Lauri Koskinen,
Hannu Tenhunen:
Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication.
ARCS 2009: 183-194 |
| 2008 |
|---|
| 76 | EE | Elena Dubrova,
Maxim Teslenko,
Hannu Tenhunen:
On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers.
DATE 2008: 1286-1291 |
| 75 | EE | Dragos Truscan,
Tiberiu Seceleanu,
Johan Lilius,
Hannu Tenhunen:
A Model-Based Design Process for the SegBus Distributed Architecture.
ECBS 2008: 307-316 |
| 74 | EE | Khalid Latif,
Moazzam Niazi,
Hannu Tenhunen,
Tiberiu Seceleanu,
Sakir Sezer:
Application development flow for on-chip distributed architectures.
SoCC 2008: 163-168 |
| 73 | EE | Sampo Tuuna,
Jouni Isoaho,
Hannu Tenhunen:
Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation.
VLSI Design 2008: 228-234 |
| 72 | EE | Roshan Weerasekera,
Dinesh Pamunuwa,
Li-Rong Zheng,
Hannu Tenhunen:
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime.
IEEE Trans. VLSI Syst. 16(5): 589-593 (2008) |
| 71 | EE | Sampo Tuuna,
Li-Rong Zheng,
Jouni Isoaho,
Hannu Tenhunen:
Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid.
IEEE Trans. VLSI Syst. 16(6): 766-770 (2008) |
| 2007 |
|---|
| 70 | EE | Yuechao Niu,
Majid Baghaei Nejad,
Hannu Tenhunen,
Li-Rong Zheng:
Design of a Digital Baseband Processor for UWB Transceiver on RFID Tag.
AINA Workshops (2) 2007: 358-361 |
| 69 | EE | Dragos Truscan,
Tiberiu Seceleanu,
Hannu Tenhunen,
Johan Lilius:
Towards a Design Methodology for Multiprocessor Platforms.
COMPSAC (1) 2007: 575-578 |
| 68 | EE | Pekka Rantala,
Jouni Isoaho,
Hannu Tenhunen:
Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip.
DSD 2007: 551-555 |
| 67 | | Pekka Rantala,
Jouni Isoaho,
Hannu Tenhunen:
Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip.
ERSA 2007: 207-210 |
| 66 | EE | Roshan Weerasekera,
Li-Rong Zheng,
Dinesh Pamunuwa,
Hannu Tenhunen:
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs.
ICCAD 2007: 212-219 |
| 65 | EE | Majid Baghaei Nejad,
Zhuo Zou,
Hannu Tenhunen,
Li-Rong Zheng:
A Novel Passive Tag with Asymmetric Wireless Link for RFID and WSN Applications.
ISCAS 2007: 1593-1596 |
| 64 | EE | Roshan Weerasekera,
Dinesh Pamunuwa,
Li-Rong Zheng,
Hannu Tenhunen:
Delay-Balanced Smart Repeaters for On-Chip Global Signaling.
VLSI Design 2007: 308-313 |
| 2006 |
|---|
| 63 | EE | Roshan Weerasekera,
Dinesh Pamunuwa,
Li-Rong Zheng,
Hannu Tenhunen:
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime.
SLIP 2006: 113-120 |
| 62 | EE | Sampo Tuuna,
Jouni Isoaho,
Hannu Tenhunen:
Analytical model for crosstalk and intersymbol interference in point-to-point buses.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1400-1410 (2006) |
| 2005 |
|---|
| 61 | | Elena Dubrova,
Maxim Teslenko,
Hannu Tenhunen:
Computing attractors in dynamic networks.
IADIS AC 2005: 535-542 |
| 60 | EE | Meigen Shen,
Li-Rong Zheng,
Esa Tjukanoff,
Jouni Isoaho,
Hannu Tenhunen:
Case study of interconnect analysis for standing wave oscillator design.
ISCAS (1) 2005: 456-459 |
| 59 | EE | Xinzhong Duo,
Li-Rong Zheng,
Mohammed Ismail,
Hannu Tenhunen:
A concurrent multi-band LNA for multi-standard radios.
ISCAS (4) 2005: 3982-3985 |
| 58 | EE | Meigen Shen,
Li-Rong Zheng,
Esa Tjukanoff,
Jouni Isoaho,
Hannu Tenhunen:
Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach.
ISQED 2005: 573-578 |
| 57 | EE | Ana Rusu,
Mohammed Ismail,
Hannu Tenhunen:
A Modified Cascaded Sigma-Delta Modulator with Improved Linearity.
ISVLSI 2005: 77-82 |
| 56 | EE | Jari Nurmi,
Jan Madsen,
Erwin Ofner,
Jouni Isoaho,
Hannu Tenhunen:
The SoC-Mobinet Model in System-on-Chip Education.
MSE 2005: 71-72 |
| 55 | EE | Roshan Weerasekera,
Li-Rong Zheng,
Dinesh Pamunuwa,
Hannu Tenhunen:
Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses.
PATMOS 2005: 277-285 |
| 54 | EE | Ahmed Amine Jerraya,
Hannu Tenhunen,
Wayne Wolf:
Guest Editors' Introduction: Multiprocessor Systems-on-Chips.
IEEE Computer 38(7): 36-40 (2005) |
| 53 | EE | Dinesh Pamunuwa,
Shauki Elassaad,
Hannu Tenhunen:
Modeling delay and noise in arbitrarily coupled RC trees.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1725-1739 (2005) |
| 52 | EE | Meigen Shen,
Jian Liu,
Li-Rong Zheng,
Esa Tjukanoff,
Hannu Tenhunen:
Robustness enhancement through chip-package co-design for high-speed electronics.
Microelectronics Journal 36(9): 846-855 (2005) |
| 2004 |
|---|
| 51 | EE | Andreas Gothenberg,
Hannu Tenhunen:
Performance analysis of sampling switches in voltage and frequency domains using Volterra series.
ISCAS (1) 2004: 765-768 |
| 50 | | Xinzhong Duo,
Li-Rong Zheng,
Hannu Tenhunen:
RF robustness enhancement through statistical analysis of chip package co-design.
ISCAS (1) 2004: 988-991 |
| 49 | EE | Meigen Shen,
Li-Rong Zheng,
Hannu Tenhunen:
Robustness Enhancement through Chip-Package Co-Design for High-Speed Electronics.
ISQED 2004: 184-189 |
| 48 | EE | Adam Strak,
Hannu Tenhunen:
Suppression of Jitter Effects in A/D Converters through Sigma-Delta Sampling.
ISVLSI 2004: 121-126 |
| 47 | EE | Ana Rusu,
Alexei Borodenkov,
Mohammed Ismail,
Hannu Tenhunen:
Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers.
PATMOS 2004: 564-573 |
| 46 | EE | Imed Ben Dhaou,
Hannu Tenhunen:
Efficient library characterization for high-level power estimation.
IEEE Trans. VLSI Syst. 12(6): 657-661 (2004) |
| 45 | EE | Dinesh Pamunuwa,
Johnny Öberg,
Li-Rong Zheng,
Mikael Millberg,
Axel Jantsch,
Hannu Tenhunen:
A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime.
Integration 38(1): 3-17 (2004) |
| 44 | EE | Axel Jantsch,
Johnny Öberg,
Hannu Tenhunen:
Special issue on networks on chip.
Journal of Systems Architecture 50(2-3): 61-63 (2004) |
| 43 | EE | Jian Liu,
Li-Rong Zheng,
Hannu Tenhunen:
Interconnect intellectual property for Network-on-Chip (NoC).
Journal of Systems Architecture 50(2-3): 65-79 (2004) |
| 2003 |
|---|
| 42 | EE | Dinesh Pamunuwa,
Shauki Elassaad,
Hannu Tenhunen:
Analytic Modeling of Interconnects for Deep Sub-Micron Circuits.
ICCAD 2003: 835-842 |
| 41 | EE | Wim Michielsen,
Li-Rong Zheng,
Hannu Tenhunen:
Analysis and design of a double tuned Clapp oscillator for multi-band multi-standard radio.
ISCAS (1) 2003: 681-684 |
| 40 | EE | Jian Liu,
Li-Rong Zheng,
Dinesh Pamunuwa,
Hannu Tenhunen:
A global wire planning scheme for Network-on-Chip.
ISCAS (4) 2003: 892-895 |
| 39 | EE | Meigen Shen,
Li-Rong Zheng,
Hannu Tenhunen:
Case study of cost and performance trade-off analysis for mixed-signal integration in system-on-chip.
ISCAS (5) 2003: 585-588 |
| 38 | EE | Jian Liu,
Meigen Shen,
Li-Rong Zheng,
Hannu Tenhunen:
System level interconnect design for network-on-chip using interconnect IPs.
SLIP 2003: 117-124 |
| 37 | EE | Dinesh Pamunuwa,
Li-Rong Zheng,
Hannu Tenhunen:
Maximizing throughput over parallel wire structures in the deep submicrometer regime.
IEEE Trans. VLSI Syst. 11(2): 224-243 (2003) |
| 2002 |
|---|
| 36 | EE | Tuomas Valtonen,
Jouni Isoaho,
Hannu Tenhunen:
The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance.
FPL 2002: 816-825 |
| 35 | EE | Hannu Tenhunen,
Dinesh Pamunuwa:
On dynamic delay and repeater insertion.
ISCAS (1) 2002: 97-100 |
| 34 | EE | Bingxin Li,
Hannu Tenhunen:
A structure of cascading multi-bit modulators without dynamic element matching or digital correction.
ISCAS (3) 2002: 711-714 |
| 33 | EE | Dinesh Pamunuwa,
Li-Rong Zheng,
Hannu Tenhunen:
Optimising bandwidth over deep sub-micron interconnect.
ISCAS (4) 2002: 193-196 |
| 32 | EE | Tuomas Valtonen,
Tero Nurmi,
Jouni Isoaho,
Hannu Tenhunen:
Interconnection of autonomous error-tolerant cells.
ISCAS (4) 2002: 473-476 |
| 31 | EE | Pasi Liljeberg,
Imed Ben Dhaou,
Juha Plosila,
Jouni Isoaho,
Hannu Tenhunen:
Interconnect peak current reduction for wavelet array processor using self-timed signaling.
ISCAS (4) 2002: 485-488 |
| 30 | EE | Dinesh Pamunuwa,
Hannu Tenhunen:
On Dynamic Delay and Repeater Insertion in Distributed Capacitively Coupled Interconnects.
ISQED 2002: 240-245 |
| 2001 |
|---|
| 29 | EE | Bingxin Li,
Hannu Tenhunen:
Sigma delta modulators using semi-uniform quantizers.
ISCAS (1) 2001: 456-459 |
| 28 | EE | T. Suutari,
Jouni Isoaho,
Hannu Tenhunen:
High-speed serial communication with error correction using 0.25 um CMOS technology.
ISCAS (4) 2001: 618-621 |
| 27 | EE | Imed Ben Dhaou,
Hannu Tenhunen,
Vijay Sundararajan,
Keshab K. Parhi:
Energy efficient signaling in DSM CMOS technology.
ISCAS (5) 2001: 411-414 |
| 26 | EE | Imed Ben Dhaou,
N. Money,
Hannu Tenhunen:
Fast low-power characterization of arithmetic units in DSM CMOS.
ISCAS (5) 2001: 531-534 |
| 25 | | Imed Ben Dhaou,
Elena Dubrova,
Hannu Tenhunen:
Power Efficient Inter-Module Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology.
ISMVL 2001: 61-66 |
| 24 | EE | Imed Ben Dhaou,
Hannu Tenhunen,
Vijay Sundararajan,
Keshab K. Parhi:
Energy Efficient Signaling in Deep Submicron CMOS Technology.
ISQED 2001: 319-324 |
| 23 | EE | Peeter Ellervee,
Hannu Tenhunen:
Digital Hardware Organization Course for SoC Program.
MSE 2001: 26-27 |
| 22 | EE | Peter Nilsson,
Petru Eles,
Hannu Tenhunen:
SOCWARE: A New Swedish Design Cluster for System-on-Chip.
MSE 2001: 44-45 |
| 21 | EE | Hannu Tenhunen,
Elena Dubrova:
SoC Masters: An International M.Sc. Program in System-on-Chip Design at KTH.
MSE 2001: 64-66 |
| 20 | EE | Dinesh Pamunuwa,
Hannu Tenhunen:
Repeater Insertion To Minimise Delay In Coupled Interconnects.
VLSI Design 2001: 513-517 |
| 2000 |
|---|
| 19 | EE | Imed Ben Dhaou,
Hannu Tenhunen:
Energy efficient high-speed on-chip signaling in deep-submicron CMOS technology.
SLIP 2000: 69-76 |
| 1999 |
|---|
| 18 | EE | Li-Rong Zheng,
Hannu Tenhunen:
Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits.
ARVLSI 1999: 123-136 |
| 17 | EE | Lihong Jia,
Yonghong Gao,
Jouni Isoaho,
Hannu Tenhunen:
Design of a super-pipelined Viterbi decoder.
ISCAS (1) 1999: 133-136 |
| 16 | EE | Li-Rong Zheng,
Hannu Tenhunen:
Effective power and ground distribution scheme for deep submicron high speed VLSI circuits.
ISCAS (1) 1999: 537-540 |
| 15 | EE | Imed Ben Dhaou,
Hannu Tenhunen:
Combinatorial architectural level power optimization for a class of orthogonal transforms.
ISCAS (1) 1999: 70-75 |
| 14 | EE | B. E. Jonsson,
Hannu Tenhunen:
A dual 3-V 32-MS/s CMOS switched-current ADC for telecommunication applications.
ISCAS (2) 1999: 343-346 |
| 13 | EE | B. E. Jonsson,
Hannu Tenhunen:
A 3 V switched-current pipelined analog-to-digital converter in a 5 V CMOS process.
ISCAS (2) 1999: 351-354 |
| 12 | EE | Thomas Meincke,
Ahmed Hemani,
Shashi Kumar,
Peeter Ellervee,
Johnny Öberg,
Thomas Olsson,
Peter Nilsson,
Dan Lindqvist,
Hannu Tenhunen:
Globally asynchronous locally synchronous architecture for large high-performance ASICs.
ISCAS (2) 1999: 512-515 |
| 11 | EE | L. Horvath,
Imed Ben Dhaou,
Hannu Tenhunen,
Jouni Isoaho:
A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T.
ISCAS (4) 1999: 382-385 |
| 10 | EE | P. Eriksson,
Hannu Tenhunen:
A model for predicting sampler RF bandwidth and conversion loss.
ISCAS (6) 1999: 18-21 |
| 9 | | Bingxin Li,
Hannu Tenhunen:
A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process.
VLSI 1999: 23-34 |
| 1996 |
|---|
| 8 | EE | Bengt Svantesson,
Ahmed Hemani,
Peeter Ellervee,
Adam Postula,
Johnny Öberg,
Axel Jantsch,
Hannu Tenhunen:
A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts.
VLSI Design 1996: 23-28 |
| 1995 |
|---|
| 7 | | M. Rinne,
T. Jarske,
Hannu Tenhunen,
Olli Vainio,
Yrjö Neuvo:
Noise Suppression System Integration Using an Analog Allpass Filter Bank.
ISCAS 1995: 1207-1210 |
| 1994 |
|---|
| 6 | EE | Axel Jantsch,
Peeter Ellervee,
Ahmed Hemani,
Johnny Öberg,
Hannu Tenhunen:
Hardware/software partitioning and minimizing memory interface traffic.
EURO-DAC 1994: 226-231 |
| 5 | | T. Saluvere,
D. Kerek,
Hannu Tenhunen:
Direct Sequence Spread Spectrum Digital Radio DSP Prototyping Using Xilinx FPGAs.
FPL 1994: 138-140 |
| 4 | | Jouni Isoaho,
Axel Jantsch,
Hannu Tenhunen:
DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques.
FPL 1994: 318-320 |
| 1993 |
|---|
| 3 | EE | Jouni Isoaho,
Jari Pasanen,
Olli Vainio,
Hannu Tenhunen:
DSP system integration and prototyping with FPGAS.
VLSI Signal Processing 6(2): 155-172 (1993) |
| 1992 |
|---|
| 2 | | Jouni Isoaho,
Arto Nummela,
Hannu Tenhunen:
Technologies and Utilization fo Field Programmable Gate Arrays.
FPL 1992: 11-25 |
| 1991 |
|---|
| 1 | | Eero Pajarre,
Tapani Ritoniemi,
Hannu Tenhunen:
Methods and Algorithms for Converting IC Designs Between Incompatible Design Systems.
ICCD 1991: 34-37 |
