Swaroop Ghosh

2009
15	EE	Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy: Coping with Variations through System-Level Design. VLSI Design 2009: 581-586
2008
14	EE	Swaroop Ghosh, Kaushik Roy: Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. ASP-DAC 2008: 635-640
13	EE	Swaroop Ghosh, Patrick Ndai, Kaushik Roy: A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking. DATE 2008: 366-371
12	EE	Swaroop Ghosh, Jung Hwan Choi, Patrick Ndai, Kaushik Roy: O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors. ISLPED 2008: 189-192
11	EE	Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy: An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs. JETC 4(3): (2008)
2007
10	EE	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. DATE 2007: 1532-1537
9	EE	Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy: Tolerance to Small Delay Defects by Adaptive Clock Stretching. IOLTS 2007: 244-252
8	EE	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-Power and testable circuit synthesis using Shannon decomposition. ACM Trans. Design Autom. Electr. Syst. 12(4): (2007)
7	EE	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1947-1956 (2007)
2006
6	EE	Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, Kaushik Roy: Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. DAC 2006: 971-976
5	EE	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. ICCAD 2006: 619-624
4	EE	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. IOLTS 2006: 31-36
3	EE	Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy: A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2934-2943 (2006)
2005
2	EE	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. Asian Test Symposium 2005: 404-409
1	EE	Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy: A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. IOLTS 2005: 287-292

Coauthor Index

1	Nilanjan Banerjee	[15]
2	Aditya Bansal	[11]
3	Swarup Bhunia	[2] [3] [4] [5] [7] [8] [9] [10]
4	Saumya Chandra	[15]
5	Jung Hwan Choi	[12]
6	Sujit Dey	[15]
7	Kee-Jong Kim	[6]
8	Jing Li	[11]
9	Saibal Mukhopadhyay	[6]
10	Patrick Ndai	[9] [12] [13]
11	Anand Raghunathan	[15]
12	Arijit Raychowdhury	[1] [3] [4]
13	Kaushik Roy	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15]