Said Hamdioui

2008
35	EE	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis: Test Set Development for Cache Memory in Modern Microprocessors. IEEE Trans. VLSI Syst. 16(6): 725-732 (2008)
2007
34		Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev: Manifestation of Precharge Faults in High Speed DRAM Devices. DDECS 2007: 179-184
33	EE	Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero: PPM Reduction on Embedded Memories in System on Chip. European Test Symposium 2007: 85-90
32	EE	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev: Optimizing Test Length for Soft Faults in DRAM Devices. VTS 2007: 59-66
2006
31	EE	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: Space of DRAM fault models and corresponding testing. DATE 2006: 1252-1257
30	EE	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor: Opens and Delay Faults in CMOS RAM Address Decoders. IEEE Trans. Computers 55(12): 1630-1639 (2006)
29	EE	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Sultan M. Al-Harbi: Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2989-2996 (2006)
2005
28	EE	Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath: Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. Asian Test Symposium 2005: 434-439
27	EE	Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor: Framework for Fault Analysis and Test Generation in DRAMs. DATE 2005: 1020-1021
26	EE	Said Hamdioui, John Eleazar Q. Delos Reyes: New data-background sequences and their industrial evaluation for word-oriented random-access memories. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 892-904 (2005)
2004
25	EE	Said Hamdioui, John Delos Reyes, Zaid Al-Ars: Evaluation of Intra-Word Faults in Word-Oriented RAMs. Asian Test Symposium 2004: 283-288
24	EE	A. J. van de Goor, Said Hamdioui, Rob Wadsworth: Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests. ITC 2004: 114-123
23	EE	A. J. van de Goor, Said Hamdioui, Zaid Al-Ars: The Effectiveness of the Scan Test and Its New Variants. MTDT 2004: 26-31
22	EE	Said Hamdioui, Georgi Gaydadjiev, A. J. van de Goor: The State-of-Art and Future Trends in Testing Embedded Memories. MTDT 2004: 54-59
21	EE	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. VTS 2004: 117-122
20	EE	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 737-757 (2004)
19	EE	Said Hamdioui, Rob Wadsworth, John Delos Reyes, A. J. van de Goor: Memory Fault Modeling Trends: A Case Study. J. Electronic Testing 20(3): 245-255 (2004)
2003
18	EE	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: March SL: A Test For All Static Linked Memory Faults. Asian Test Symposium 2003: 372-377
17	EE	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: A Fault Primitive Based Analysis of Linked Faults in RAMs. MTDT 2003: 33-
16	EE	Said Hamdioui, A. J. van de Goor, Mike Rodgers: Detecting Intra-Word Faults in Word-Oriented Memories. VTS 2003: 241-247
15	EE	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. J. Electronic Testing 19(2): 195-205 (2003)
2002
14	EE	Said Hamdioui, A. J. van de Goor, Mike Rodgers: March SS: A Test for All Static Simple RAM Faults. MTDT 2002: 95-100
13	EE	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor: Testing Static and Dynamic Faults in Random Access Memories. VTS 2002: 395-400
12	EE	Said Hamdioui, A. J. van de Goor: Efficient Tests for Realistic Faults in Dual-Port SRAMs. IEEE Trans. Computers 51(5): 460-473 (2002)
11	EE	Said Hamdioui, A. J. van de Goor: Thorough testing of any multiport memory with linear tests. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 217-231 (2002)
2001
10	EE	Said Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers: Detecting Unique Faults in Multi-port SRAMs. Asian Test Symposium 2001: 37-42
9	EE	Said Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers: Realistic Fault Models and Test Procedures for Multi-Port SRAMs. MTDT 2001: 65-72
2000
8	EE	Said Hamdioui, A. J. van de Goor: An experimental analysis of spot defects in SRAMs: realistic fault models and tests. Asian Test Symposium 2000: 131-138
7	EE	Said Hamdioui, A. J. van de Goor, Mike Rodgers, David Eastwick: March Tests for Realistic Faults in Two-Port Memories. MTDT 2000: 73-78
6	EE	Said Hamdioui, A. J. van de Goor: Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy. J. Electronic Testing 16(5): 487-498 (2000)
1999
5	EE	Said Hamdioui, A. J. van de Goor: March Tests for Word-Oriented Two-Port Memories. Asian Test Symposium 1999: 53-
4		Said Hamdioui, A. J. van de Goor: Port interference faults in two-port memories. ITC 1999: 1001-1010
1998
3	EE	Said Hamdioui, A. J. van de Goor: Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories. Asian Test Symposium 1998: 340-347
2	EE	Said Hamdioui, A. J. van de Goor: Consequences of port restrictions on testing two-port memories. ITC 1998: 63-72
1	EE	A. J. van de Goor, Said Hamdioui: Fault Models and Tests for Two-Port Memories. VTS 1998: 401-410

Coauthor Index

1	Zaid Al-Ars	[13] [15] [17] [18] [20] [21] [23] [25] [27] [28] [29] [30] [31] [32] [33] [34] [35]
2	Sultan M. Al-Harbi	[29]
3	Jose Calero	[33]
4	David Eastwick	[7] [9] [10]
5	Georgi Gaydadjiev (G. N. Gaydadjiev)	[22] [32] [34] [35]
6	A. J. van de Goor	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [27] [29] [30] [31]
7	Javier Jiménez	[33]
8	Georg Mueller	[27]
9	John Delos Reyes	[19] [25]
10	John Eleazar Q. Delos Reyes	[26]
11	Mike Rodgers	[7] [9] [10] [14] [15] [16] [18] [20]
12	Stamatis Vassiliadis	[35]
13	Jörg E. Vollrath	[28]
14	Rob Wadsworth	[19] [24]

Colors in the list of coauthors