2009 |
29 | EE | Bo-Zhou Chen,
Hung-Ming Chen,
Li-Da Huang,
Po-Cheng Pan:
A stochastic-based efficient critical area extractor on OpenAccess platform.
ACM Great Lakes Symposium on VLSI 2009: 197-202 |
28 | EE | Hsin-Hua Pan,
Hung-Ming Chen,
Chia-Yi Chang:
Buffer/flip-flop block planning for power-integrity-driven floorplanning.
ISQED 2009: 488-493 |
2008 |
27 | EE | Lun-Chun Wei,
Hung-Ming Chen,
Li-Da Huang,
Sarah Songjie Xu:
Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow.
ACM Great Lakes Symposium on VLSI 2008: 359-362 |
26 | EE | Bruce Tseng,
Hung-Ming Chen:
Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations.
ISPD 2008: 23-30 |
25 | EE | Ming-Fang Lai,
Hung-Ming Chen:
An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign.
ISQED 2008: 604-607 |
24 | EE | Chao-Hung Lu,
Hung-Ming Chen,
Chien-Nan Jimmy Liu:
Effective decap insertion in area-array SoC floorplan design.
ACM Trans. Design Autom. Electr. Syst. 13(4): (2008) |
23 | EE | Hung-Ming Chen,
Yu-Chin Lin:
Web-FEM: An internet-based finite-element analysis framework with 3D graphics and parallel computing environment.
Advances in Engineering Software 39(1): 55-68 (2008) |
22 | EE | Chao-Hung Lu,
Hung-Ming Chen,
Chien-Nan Jimmy Liu:
An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning.
J. Inf. Sci. Eng. 24(1): 115-127 (2008) |
2007 |
21 | EE | Chao-Hung Lu,
Hung-Ming Chen,
Chien-Nan Jimmy Liu:
On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design.
ASP-DAC 2007: 792-797 |
20 | EE | Ren-Jie Lee,
Ming-Fang Lai,
Hung-Ming Chen:
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign.
ASP-DAC 2007: 804-809 |
19 | EE | Chia-Yi Lin,
Hung-Ming Chen:
A selective pattern-compression scheme for power and test-data reduction.
ICCAD 2007: 520-525 |
18 | EE | Hung-Ming Chen,
Bo-Fu Liu,
Hui-Ling Huang,
Shiow-Fen Hwang,
Shinn-Ying Ho:
SODOCK: Swarm optimization for highly flexible protein-ligand docking.
Journal of Computational Chemistry 28(2): 612-623 (2007) |
2006 |
17 | EE | Li-Chung Hsu,
Hung-Ming Chen:
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design.
ISQED 2006: 451-456 |
16 | EE | Shinn-Ying Ho,
Chih-Hung Hsieh,
Kuan-Wei Chen,
Hui-Ling Huang,
Hung-Ming Chen,
Shinn-Jang Ho:
Scoring Method for Tumor Prediction from Microarray Data Using an Evolutionary Fuzzy Classifier.
PAKDD 2006: 520-529 |
15 | EE | Hung-Ming Chen,
I-Min Liu,
Martin D. F. Wong:
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2552-2556 (2006) |
14 | EE | Po-Hung Chen,
Hung-Ming Chen,
Kuo-Jui Hung,
Wen-Hsien Fang,
Mon-Chau Shie,
Feipei Lai:
Markov model fuzzy-reasoning based algorithm for fast block motion estimation.
J. Visual Communication and Image Representation 17(1): 131-142 (2006) |
2005 |
13 | EE | Shinri-Ying Ho,
Chong-Cheng Lee,
Hung-Ming Chen,
Hui-Ling Huang:
Efficient gene selection for classification of microarray data.
Congress on Evolutionary Computation 2005: 1753-1760 |
12 | EE | Bo-Fu Liu,
Hung-Ming Chen,
Hui-Ling Huang,
Shiow-Fen Hwang,
Shinn-Ying Ho:
Flexible protein-ligand docking using particle swarm optimization.
Congress on Evolutionary Computation 2005: 251-258 |
11 | EE | Bo-Fu Liu,
Hung-Ming Chen,
Jian-Hung Chen,
Shiow-Fen Hwang,
Shinn-Ying Ho:
MeSwarm: memetic particle swarm optimization.
GECCO 2005: 267-268 |
10 | EE | Muzhou Shao,
Youxin Gao,
Li-Pen Yuan,
Hung-Ming Chen,
Martin D. F. Wong:
Current Calculation on VLSI Signal Interconnects.
ISQED 2005: 580-585 |
9 | EE | Hung-Ming Chen,
Li-Da Huang,
I-Min Liu,
Martin D. F. Wong:
Simultaneous power supply planning and noise avoidance in floorplan design.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 578-587 (2005) |
8 | EE | Jian-Hung Chen,
Hung-Ming Chen,
Shinn-Ying Ho:
Design of nearest neighbor classifiers: multi-objective approach.
Int. J. Approx. Reasoning 40(1-2): 3-22 (2005) |
2004 |
7 | EE | Hung-Ming Chen,
I-Min Liu,
Martin D. F. Wong,
Muzhou Shao,
Li-Da Huang:
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design.
ICCD 2004: 562-567 |
6 | EE | Jian-Hung Chen,
Hung-Ming Chen,
Shinn-Ying Ho:
Design of Nearest Neighbor Classifiers Using an Intelligent Multi-objective Evolutionary Algorithm.
PRICAI 2004: 262-271 |
5 | EE | Shinn-Ying Ho,
Hung-Ming Chen,
Shinn-Jang Ho,
Tai-Kang Chen:
Design of accurate classifiers with a compact fuzzy-rule base using an evolutionary scatter partition of feature space.
IEEE Transactions on Systems, Man, and Cybernetics, Part B 34(2): 1031-1044 (2004) |
2003 |
4 | EE | Li-Da Huang,
Hung-Ming Chen,
D. F. Wong:
Global Wire Bus Configuration with Minimum Delay Uncertainty.
DATE 2003: 10050-10055 |
2001 |
3 | EE | Hung-Ming Chen,
D. F. Wong,
Wai-Kei Mak,
Hannah Honghua Yang:
Faster and more accurate wiring evaluation in interconnect-centric floorplanning.
ACM Great Lakes Symposium on VLSI 2001: 62-67 |
2 | EE | I-Min Liu,
Hung-Ming Chen,
Tan-Li Chou,
Adnan Aziz,
D. F. Wong:
Integrated power supply planning and floorplanning.
ASP-DAC 2001: 589-594 |
1999 |
1 | EE | Hung-Ming Chen,
Hai Zhou,
Fung Yu Young,
D. F. Wong,
Hannah Honghua Yang,
Naveed A. Sherwani:
Integrated floorplanning and interconnect planning.
ICCAD 1999: 354-357 |