| 2009 |
|---|
| 237 | EE | Daniel Große,
Robert Wille,
Ulrich Kühne,
Rolf Drechsler:
Contradictory antecedent debugging in bounded model checking.
ACM Great Lakes Symposium on VLSI 2009: 173-176 |
| 236 | EE | Robert Wille,
Daniel Große,
Gerhard W. Dueck,
Rolf Drechsler:
Reversible Logic Synthesis with Output Permutation.
VLSI Design 2009: 189-194 |
| 2008 |
|---|
| 235 | | Mario Giacobini,
Anthony Brabazon,
Stefano Cagnoni,
Gianni Di Caro,
Rolf Drechsler,
Anikó Ekárt,
Anna Esparcia-Alcázar,
Muddassar Farooq,
Andreas Fink,
Jon McCormack,
Michael O'Neill,
Juan Romero,
Franz Rothlauf,
Giovanni Squillero,
Sima Uyar,
Shengxiang Yang:
Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings
Springer 2008 |
| 234 | EE | André Sülflow,
Görschwin Fey,
Roderick Bloem,
Rolf Drechsler:
Using unsatisfiable cores to debug multiple design errors.
ACM Great Lakes Symposium on VLSI 2008: 77-82 |
| 233 | EE | Sujan Pandey,
Rolf Drechsler:
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival.
ASP-DAC 2008: 601-606 |
| 232 | EE | Sujan Pandey,
Rolf Drechsler:
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs.
DATE 2008: 206-211 |
| 231 | EE | Frank Rogin,
Thomas Klotz,
Görschwin Fey,
Rolf Drechsler,
Steffen Rülke:
Automatic Generation of Complex Properties for Hardware Designs.
DATE 2008: 545-548 |
| 230 | EE | Daniel Tille,
Rolf Drechsler:
Incremental SAT Instance Generation for SAT-based ATPG.
DDECS 2008: 68-73 |
| 229 | EE | Daniel Große,
Robert Wille,
Robert Siegmund,
Rolf Drechsler:
Contradiction Analysis for Constraint-based Random Simulation.
FDL 2008: 130-135 |
| 228 | EE | Sujan Pandey,
Rolf Drechsler,
Tudor Murgan,
Manfred Glesner:
Process variations aware robust on-chip bus architecture synthesis for MPSoCs.
ISCAS 2008: 2989-2992 |
| 227 | EE | Daniel Große,
Robert Wille,
Gerhard W. Dueck,
Rolf Drechsler:
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares.
ISMVL 2008: 214-219 |
| 226 | EE | Robert Wille,
Daniel Große,
Lisa Teuber,
Gerhard W. Dueck,
Rolf Drechsler:
RevLib: An Online Resource for Reversible Functions and Reversible Circuits.
ISMVL 2008: 220-225 |
| 225 | EE | Doina Logofatu,
Rolf Drechsler:
Comparative Study by Solving the Test Compaction Problem.
ISMVL 2008: 44-49 |
| 224 | EE | Stephan Eggersglüß,
Rolf Drechsler:
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults.
ISMVL 2008: 94-99 |
| 223 | EE | Murthy Palla,
Jens Bargfrede,
Klaus Koch,
Walter Anheier,
Rolf Drechsler:
Adaptive Branch and Bound Using SAT to Estimate False Crosstalk.
ISQED 2008: 508-513 |
| 222 | EE | Görschwin Fey,
Rolf Drechsler:
A Basis for Formal Robustness Checking.
ISQED 2008: 784-789 |
| 221 | EE | Robert Wille,
Daniel Große,
Mathias Soeken,
Rolf Drechsler:
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability.
ISVLSI 2008: 411-416 |
| 220 | EE | Görschwin Fey,
Stefan Staber,
Roderick Bloem,
Rolf Drechsler:
Automatic Fault Localization for Property Checking.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1138-1149 (2008) |
| 219 | EE | Anna Bernasconi,
Valentina Ciriani,
Rolf Drechsler,
Tiziano Villa:
Logic Minimization and Testability of 2-SPP Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1190-1202 (2008) |
| 218 | EE | Daniel Große,
Ulrich Kühne,
Rolf Drechsler:
Analyzing Functional Coverage in Bounded Model Checking.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1305-1314 (2008) |
| 217 | EE | Rolf Drechsler,
Stephan Eggersglüß,
Görschwin Fey,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel,
Daniel Tille:
On Acceleration of SAT-Based ATPG for Industrial Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1329-1333 (2008) |
| 216 | EE | Görschwin Fey,
Anna Bernasconi,
Valentina Ciriani,
Rolf Drechsler:
On the construction of small fully testable circuits with low depth.
Microprocessors and Microsystems - Embedded Hardware Design 32(5-6): 263-269 (2008) |
| 215 | EE | Sebastian Kinder,
Rolf Drechsler:
Modeling and proving functional completeness in formal verification of counting heads.
STTT 10(6): 521-534 (2008) |
| 2007 |
|---|
| 214 | | Mario Giacobini,
Anthony Brabazon,
Stefano Cagnoni,
Gianni Di Caro,
Rolf Drechsler,
Muddassar Farooq,
Andreas Fink,
Evelyne Lutton,
Penousal Machado,
Stefan Minner,
Michael O'Neill,
Juan Romero,
Franz Rothlauf,
Giovanni Squillero,
Hideyuki Takagi,
Sima Uyar,
Shengxiang Yang:
Applications of Evolutinary Computing, EvoWorkshops 2007: EvoCoMnet, EvoFIN, EvoIASP,EvoINTERACTION, EvoMUSART, EvoSTOC and EvoTransLog, Valencia, Spain, April11-13, 2007, Proceedings.
Springer 2007 |
| 213 | EE | Daniel Große,
Rüdiger Ebendt,
Rolf Drechsler:
Improvements for constraint solving in the systemc verification library.
ACM Great Lakes Symposium on VLSI 2007: 493-496 |
| 212 | EE | Daniel Große,
Xiaobo Chen,
Gerhard W. Dueck,
Rolf Drechsler:
Exact sat-based toffoli network synthesis.
ACM Great Lakes Symposium on VLSI 2007: 96-101 |
| 211 | EE | Daniel Große,
Ulrich Kühne,
Rolf Drechsler:
Estimating functional coverage in bounded model checking.
DATE 2007: 1176-1181 |
| 210 | | Daniel Tille,
Görschwin Fey,
Rolf Drechsler:
Instance Generation for SAT-based ATPG.
DDECS 2007: 153-156 |
| 209 | EE | Sebastian Kinder,
Rolf Drechsler:
Proving Completeness of Properties in Formal Verification of Counting Heads for Railways.
DSD 2007: 396-403 |
| 208 | EE | Görschwin Fey,
Anna Bernasconi,
Valentina Ciriani,
Rolf Drechsler:
On the Construction of Small Fully Testable Circuits with Low Depth.
DSD 2007: 563-569 |
| 207 | EE | Frank Rogin,
Christian Genz,
Rolf Drechsler,
Steffen Rülke:
An Integrated SystemC Debugging Environment.
FDL 2007: 140-145 |
| 206 | EE | Daniel Große,
Hernan Peraza,
Wolfgang Klingauf,
Rolf Drechsler:
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques.
FDL 2007: 146-151 |
| 205 | | Rolf Drechsler,
Andreas Breiter:
Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?.
ICSOFT (SE) 2007: 409-416 |
| 204 | EE | Stephan Eggersglüß,
Görschwin Fey,
Rolf Drechsler:
SAT-based ATPG for Path Delay Faults in Sequential Circuits.
ISCAS 2007: 3671-3674 |
| 203 | EE | Christian Genz,
Rolf Drechsler,
Gerhard Angst,
Lothar Linhard:
Visualization of SystemC Designs.
ISCAS 2007: 413-416 |
| 202 | EE | André Sülflow,
Rolf Drechsler:
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC.
ISMVL 2007: 42 |
| 201 | EE | Mahsan Amoui,
Daniel Große,
Mitchell A. Thornton,
Rolf Drechsler:
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL.
ISMVL 2007: 50 |
| 200 | EE | Stephan Eggersglüß,
Daniel Tille,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
Experimental Studies on SAT-Based ATPG for Gate Delay Faults.
ISMVL 2007: 6 |
| 199 | EE | Ulrich Kühne,
Daniel Große,
Rolf Drechsler:
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation.
ISVLSI 2007: 165-170 |
| 198 | EE | Stephan Eggersglüß,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults.
MEMOCODE 2007: 181-187 |
| 197 | EE | Görschwin Fey,
Tim Warode,
Rolf Drechsler:
Reusing Learned Information in SAT-based ATPG.
VLSI Design 2007: 69-76 |
| 196 | EE | Sujan Pandey,
Christian Genz,
Rolf Drechsler:
Co-synthesis of custom on-chip bus and memory for MPSoC architectures.
VLSI-SoC 2007: 304-307 |
| 195 | EE | Robert Wille,
Görschwin Fey,
Daniel Große,
Stephan Eggersglüß,
Rolf Drechsler:
SWORD: A SAT like prover using word level information.
VLSI-SoC 2007: 88-93 |
| 194 | EE | Sabine Glesner,
Jens Knoop,
Rolf Drechsler:
Preface.
Electr. Notes Theor. Comput. Sci. 190(4): 1-2 (2007) |
| 193 | EE | Beate Muranko,
Rolf Drechsler:
Technische Dokumentation von Soft- und Hardware in Eingebetteten Systemen (Technical Documentation of Soft- and Hardware in Embedded Systems).
it - Information Technology 49(2): 110- (2007) |
| 2006 |
|---|
| 192 | | Franz Rothlauf,
Jürgen Branke,
Stefano Cagnoni,
Ernesto Costa,
Carlos Cotta,
Rolf Drechsler,
Evelyne Lutton,
Penousal Machado,
Jason H. Moore,
Juan Romero,
George D. Smith,
Giovanni Squillero,
Hideyuki Takagi:
Applications of Evolutionary Computing, EvoWorkshops 2006: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, and EvoSTOC, Budapest, Hungary, April 10-12, 2006, Proceedings
Springer 2006 |
| 191 | EE | Daniel Große,
Ulrich Kühne,
Rolf Drechsler:
HW/SW co-verification of embedded systems using bounded model checking.
ACM Great Lakes Symposium on VLSI 2006: 43-48 |
| 190 | EE | Görschwin Fey,
Sean Safarpour,
Andreas G. Veneris,
Rolf Drechsler:
On the relation between simulation-based and SAT-based diagnosis.
DATE 2006: 1139-1144 |
| 189 | EE | Görschwin Fey,
Daniel Große,
Rolf Drechsler:
Avoiding false negatives in formal verification for protocol-driven blocks.
DATE 2006: 1225-1226 |
| 188 | EE | Anna Bernasconi,
Valentina Ciriani,
Rolf Drechsler,
Tiziano Villa:
Efficient minimization of fully testable 2-SPP networks.
DATE 2006: 1300-1305 |
| 187 | EE | André Sülflow,
Nicole Drechsler,
Rolf Drechsler:
Robust Multi-Objective Optimization in High Dimensional Spaces.
EMO 2006: 715-726 |
| 186 | EE | Doina Logofatu,
Rolf Drechsler:
Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion.
EvoWorkshops 2006: 320-331 |
| 185 | EE | Stefan Staber,
Görschwin Fey,
Roderick Bloem,
Rolf Drechsler:
Automatic Fault Localization for Property Checking.
Haifa Verification Conference 2006: 50-64 |
| 184 | EE | Sean Safarpour,
Andreas G. Veneris,
Rolf Drechsler:
Integrating observability don't cares in all-solution SAT solvers.
ISCAS 2006 |
| 183 | EE | Rüdiger Ebendt,
Rolf Drechsler:
On the sensitivity of BDDs with respect to path-related objective functions.
ISCAS 2006 |
| 182 | EE | Görschwin Fey,
Junhao Shi,
Rolf Drechsler:
Efficiency of Multi-Valued Encoding in SAT-based ATPG.
ISMVL 2006: 25 |
| 181 | EE | Christian Genz,
Rolf Drechsler:
System Exploration of SystemC Designs.
ISVLSI 2006: 335-342 |
| 180 | EE | Rüdiger Ebendt,
Rolf Drechsler:
A Framework for Quasi-exact Optimization Using Relaxed Best-First Search.
KI 2006: 331-345 |
| 179 | EE | Rolf Drechsler,
Görschwin Fey:
Automatic Test Pattern Generation.
SFM 2006: 30-55 |
| 178 | EE | Rolf Drechsler,
Görschwin Fey,
Sebastian Kinder:
An Integrated Approach for Combining BDD and SAT Provers.
VLSI Design 2006: 237-242 |
| 177 | EE | Beate Muranko,
Rolf Drechsler:
Technical Documentation of Software and Hardware in Embedded Systems.
VLSI-SoC 2006: 261-266 |
| 176 | EE | Görschwin Fey,
Rolf Drechsler:
Minimizing the number of paths in BDDs: Theory and algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 4-11 (2006) |
| 175 | EE | Valentina Ciriani,
Anna Bernasconi,
Rolf Drechsler:
Testability of SPP Three-Level Logic Networks in Static Fault Models.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2241-2248 (2006) |
| 174 | EE | Rüdiger Ebendt,
Rolf Drechsler:
Effect of improved lower bounds in dynamic BDD reordering.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 902-909 (2006) |
| 2005 |
|---|
| 173 | | Franz Rothlauf,
Jürgen Branke,
Stefano Cagnoni,
David W. Corne,
Rolf Drechsler,
Yaochu Jin,
Penousal Machado,
Elena Marchiori,
Juan Romero,
George D. Smith,
Giovanni Squillero:
Applications of Evolutionary Computing, EvoWorkshops 2005: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Lausanne, Switzerland, March 30 - April 1, 2005, Proceedings
Springer 2005 |
| 172 | EE | Sean Safarpour,
Görschwin Fey,
Andreas G. Veneris,
Rolf Drechsler:
Utilizing don't care states in SAT-based bounded sequential problems.
ACM Great Lakes Symposium on VLSI 2005: 264-269 |
| 171 | EE | Junhao Shi,
Görschwin Fey,
Rolf Drechsler:
Bridging fault testability of BDD circuits.
ASP-DAC 2005: 188-191 |
| 170 | EE | Rüdiger Ebendt,
Rolf Drechsler:
Lower bounds for dynamic BDD reordering.
ASP-DAC 2005: 579-582 |
| 169 | EE | Daniel Große,
Rolf Drechsler:
Acceleration of SAT-Based Iterative Property Checking.
CHARME 2005: 349-353 |
| 168 | | Daniel Große,
Ulrich Kühne,
Rolf Drechsler:
Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors.
GI Jahrestagung (1) 2005: 308-312 |
| 167 | | Moayad Fahim Ali,
Sean Safarpour,
Andreas G. Veneris,
Magdy S. Abadir,
Rolf Drechsler:
Post-verification debugging of hierarchical designs.
ICCAD 2005: 871-876 |
| 166 | EE | Rolf Drechsler,
Görschwin Fey,
Christian Genz,
Daniel Große:
SyCE: An Integrated Environment for System Design in SystemC.
IEEE International Workshop on Rapid System Prototyping 2005: 258-260 |
| 165 | EE | Daniel Große,
Rolf Drechsler:
CheckSyC: an efficient property checker for RTL SystemC designs.
ISCAS (4) 2005: 4167-4170 |
| 164 | EE | Sebastian Kinder,
Görschwin Fey,
Rolf Drechsler:
Controlling the Memory During Manipulation of Word-Level Decision Diagrams.
ISMVL 2005: 250-255 |
| 163 | EE | Junhao Shi,
Görschwin Fey,
Rolf Drechsler,
Andreas Glowatz,
Friedrich Hapke,
Jürgen Schlöffel:
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits.
ISVLSI 2005: 212-217 |
| 162 | EE | Rüdiger Ebendt,
Rolf Drechsler:
Quasi-Exact BDD Minimization Using Relaxed Best-First Search.
ISVLSI 2005: 59-64 |
| 161 | EE | Daniel Große,
Ulrich Kühne,
Rolf Drechsler:
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking.
MTV 2005: 133-137 |
| 160 | EE | Moayad Fahim Ali,
Sean Safarpour,
Andreas G. Veneris,
Magdy S. Abadir,
Rolf Drechsler:
Post-Verification Debugging of Hierarchical Designs.
MTV 2005: 42-47 |
| 159 | EE | Rüdiger Ebendt,
Rolf Drechsler:
Exact BDD Minimization for Path-Related Objective Functions.
VLSI-SoC 2005: 299-315 |
| 158 | EE | Rüdiger Ebendt,
Wolfgang Günther,
Rolf Drechsler:
Combining ordered best-first search with branch and bound for exact BDD minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1515-1529 (2005) |
| 2004 |
|---|
| 157 | | Günther R. Raidl,
Stefano Cagnoni,
Jürgen Branke,
David Corne,
Rolf Drechsler,
Yaochu Jin,
Colin G. Johnson,
Penousal Machado,
Elena Marchiori,
Franz Rothlauf,
George D. Smith,
Giovanni Squillero:
Applications of Evolutionary Computing, EvoWorkshops 2004: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Coimbra, Portugal, April 5-7, 2004, Proceedings
Springer 2004 |
| 156 | EE | Görschwin Fey,
Rolf Drechsler:
Improving simulation-based verification by means of formal methods.
ASP-DAC 2004: 640-643 |
| 155 | EE | Rüdiger Ebendt,
Wolfgang Günther,
Rolf Drechsler:
Minimization of the expected path length in BDDs based on local changes.
ASP-DAC 2004: 865-870 |
| 154 | EE | Rüdiger Ebendt,
Wolfgang Günther,
Rolf Drechsler:
Combining ordered best-first search with branch and bound for exact BDD minimization.
ASP-DAC 2004: 875-878 |
| 153 | EE | Sean Safarpour,
Andreas G. Veneris,
Rolf Drechsler,
Joanne Lee:
Managing Don't Cares in Boolean Satisfiability.
DATE 2004: 260-265 |
| 152 | EE | Görschwin Fey,
Junhao Shi,
Rolf Drechsler:
BDD Circuit Optimization for Path Delay Fault Testability.
DSD 2004: 168-172 |
| 151 | EE | Nicole Drechsler,
Mario Hilgemeier,
Görschwin Fey,
Rolf Drechsler:
Disjoint Sum of Product Minimization by Evolutionary Algorithms.
EvoWorkshops 2004: 198-207 |
| 150 | EE | Moayad Fahim Ali,
Andreas G. Veneris,
Alexander Smith,
Sean Safarpour,
Rolf Drechsler,
Magdy S. Abadir:
Debugging sequential circuits using Boolean satisfiability.
ICCAD 2004: 204-209 |
| 149 | EE | Rolf Drechsler:
Towards Formal Verification on the System Level.
IEEE International Workshop on Rapid System Prototyping 2004: 2-5 |
| 148 | EE | Dragan Jankovic,
Radomir S. Stankovic,
Rolf Drechsler:
Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Propertie.
ISMVL 2004: 223-228 |
| 147 | EE | Görschwin Fey,
Rolf Drechsler,
Maciej J. Ciesielski:
Algorithms for Taylor Expansion Diagrams.
ISMVL 2004: 235-240 |
| 146 | EE | Daniel Große,
Rolf Drechsler:
Checkers for SystemC designs.
MEMOCODE 2004: 171-178 |
| 145 | EE | Moayad Fahim Ali,
Andreas G. Veneris,
Sean Safarpour,
Magdy S. Abadir,
Freescale Semiconductor,
Rolf Drechsler,
Alexander Smith:
Debugging Sequential Circuits Using Boolean Satisfiability.
MTV 2004: 44-49 |
| 144 | EE | Rolf Drechsler,
Junhao Shi,
Görschwin Fey:
Synthesis of fully testable circuits from BDDs.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(3): 440-443 (2004) |
| 2003 |
|---|
| 143 | EE | Rolf Drechsler,
Junhao Shi,
Görschwin Fey:
MuTaTe: an efficient design for testability technique for multiplexor based circuits.
ACM Great Lakes Symposium on VLSI 2003: 80-83 |
| 142 | | Rolf Drechsler,
Nicole Drechsler:
Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms.
Applied Informatics 2003: 109-114 |
| 141 | EE | Junhao Shi,
Görschwin Fey,
Rolf Drechsler:
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability.
Asian Test Symposium 2003: 290-293 |
| 140 | EE | Rüdiger Ebendt,
Wolfgang Günther,
Rolf Drechsler:
Combination of Lower Bounds in Exact BDD Minimization.
DATE 2003: 10758-10763 |
| 139 | EE | Mario Hilgemeier,
Nicole Drechsler,
Rolf Drechsler:
Fast Heuristics for the Edge Coloring of Large Graphs.
DSD 2003: 230-239 |
| 138 | EE | Rolf Drechsler,
Nicole Drechsler:
GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages.
EvoWorkshops 2003: 378-387 |
| 137 | EE | Daniel Große,
Rolf Drechsler,
Lothar Linhard,
Gerhard Angst:
Efficient Automatic Visualization of SystemC Designs.
FDL 2003: 646-658 |
| 136 | EE | Rolf Drechsler:
Synthesizing checkers for on-line verification of System-on-Chip designs.
ISCAS (4) 2003: 748-751 |
| 135 | EE | Daniel Große,
Rolf Drechsler:
Formal verification of LTL formulas for SystemC designs.
ISCAS (5) 2003: 245-248 |
| 134 | EE | Denis V. Popel,
Rolf Drechsler:
Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely Specified Functions.
ISMVL 2003: 241-246 |
| 133 | EE | Daniel Große,
Görschwin Fey,
Rolf Drechsler:
Modeling Multi-Valued Circuits in SystemC.
ISMVL 2003: 281-286 |
| 132 | EE | Görschwin Fey,
Sebastian Kinder,
Rolf Drechsler:
Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques.
ISMVL 2003: 361-366 |
| 131 | EE | D. Michael Miller,
Rolf Drechsler:
Augmented Sifting of Multiple-Valued Decision Diagrams.
ISMVL 2003: 375-382 |
| 130 | EE | Görschwin Fey,
Rolf Drechsler:
Finding Good Counter-Examples to Aid Design Verification.
MEMOCODE 2003: 51- |
| 129 | | Valentina Ciriani,
Anna Bernasconi,
Rolf Drechsler:
Testability of SPP Three-Level Logic Networks.
VLSI-SOC 2003: 331-336 |
| 128 | | Nicole Drechsler,
Rolf Drechsler:
Exploration of Sequential Depth by Evolutionary Algorithms.
VLSI-SOC 2003: 81-85 |
| 127 | | Martin Keim,
Rolf Drechsler,
Bernd Becker,
Michael Martin,
Paul Molitor:
Polynomial Formal Verification of Multipliers.
Formal Methods in System Design 22(1): 39-58 (2003) |
| 126 | EE | Frank Schmiedle,
Rolf Drechsler,
Bernd Becker:
Exact Routing with Search Space Reduction.
IEEE Trans. Computers 52(6): 815-825 (2003) |
| 125 | EE | Wolfgang Günther,
Rolf Drechsler:
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams.
IEEE Trans. Computers 52(9): 1196-1209 (2003) |
| 124 | EE | Rüdiger Ebendt,
Wolfgang Günther,
Rolf Drechsler:
An improved branch and bound algorithm for exact BDD minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(12): 1657-1663 (2003) |
| 123 | EE | Rolf Drechsler,
Wolfgang Günther,
Thomas Eschbach,
Lothar Linhard,
Gerhard Angst:
Recursive bi-partitioning of netlists for large number of partitions.
Journal of Systems Architecture 49(12-15): 521-528 (2003) |
| 122 | | Daniel Große,
Rolf Drechsler:
Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC.
it - Information Technology 45(4): 219-226 (2003) |
| 2002 |
|---|
| 121 | EE | Whitney J. Townsend,
Mitchell A. Thornton,
Rolf Drechsler,
D. Michael Miller:
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations.
ACM Great Lakes Symposium on VLSI 2002: 178-183 |
| 120 | EE | Dragan Jankovic,
Radomir S. Stankovic,
Rolf Drechsler:
Decision Diagram Optimization Using Copy Properties.
DSD 2002: 236-243 |
| 119 | EE | Rolf Drechsler,
Daniel Große:
Reachability Analysis for Formal Verification of SystemC.
DSD 2002: 337-340 |
| 118 | EE | Rolf Drechsler,
Wolfgang Günther,
Thomas Eschbach,
Lothar Linhard,
Gerhard Angst:
Recursive Bi-Partitioning of Netlists for Large Number of Partitions.
DSD 2002: 38-44 |
| 117 | EE | Thomas Eschbach,
Wolfgang Günther,
Rolf Drechsler,
Bernd Becker:
Crossing Reduction by Windows Optimization.
Graph Drawing 2002: 285-294 |
| 116 | EE | Mikael Kerttu,
Per Lindgren,
Mitchell A. Thornton,
Rolf Drechsler:
Switching activity estimation of finite state machines for low power synthesis.
ISCAS (4) 2002: 65-68 |
| 115 | EE | D. Michael Miller,
Rolf Drechsler:
On the Construction of Multiple-Valued Decision Diagrams.
ISMVL 2002: 245-253 |
| 114 | EE | Rolf Drechsler:
Evaluation of Static Variable Ordering Heuristics for MDD Construction.
ISMVL 2002: 254-260 |
| 113 | EE | Sherief Reda,
Rolf Drechsler,
Alex Orailoglu:
On the Relation between SAT and BDDs for Equivalence Checking.
ISQED 2002: 394-399 |
| 112 | EE | Mitchell A. Thornton,
Rolf Drechsler,
D. Michael Miller:
Multi-Output Timed Shannon Circuits.
ISVLSI 2002: 47-52 |
| 111 | | Mikael Kerttu,
Per Lindgren,
Rolf Drechsler,
Mitchell A. Thornton:
Low Power Optimization Techniques for BDD Mapped Finite State Machines.
IWLS 2002: 143-148 |
| 110 | EE | Raik Brinkmann,
Rolf Drechsler:
RTL-Datapath Verification using Integer Linear Programming.
VLSI Design 2002: 741-746 |
| 109 | | Frank Schmiedle,
Nicole Drechsler,
Daniel Große,
Rolf Drechsler:
Heuristic Learning Based on Genetic Programming.
Genetic Programming and Evolvable Machines 3(4): 363-388 (2002) |
| 108 | EE | Wolfgang Günther,
Rolf Drechsler:
Minimization of free BDDs.
Integration 32(1-2): 41-59 (2002) |
| 107 | EE | Rolf Drechsler:
Verifying integrity of decision diagrams.
Integration 32(1-2): 61-75 (2002) |
| 106 | EE | Rolf Drechsler,
Wolfgang Günther,
Stefan Höreth:
Minimization of Word-Level Decision Diagrams.
Integration 33(1-2): 39-70 (2002) |
| 2001 |
|---|
| 105 | EE | Per Lindgren,
Mikael Kerttu,
Mitchell A. Thornton,
Rolf Drechsler:
Low power optimization technique for BDD mapped circuits.
ASP-DAC 2001: 615-621 |
| 104 | EE | Mitchell A. Thornton,
Rolf Drechsler:
Spectral decision diagrams using graph transformations.
DATE 2001: 713-719 |
| 103 | EE | Rolf Drechsler,
Wolfgang Günther,
Lothar Linhard,
Gerhard Angst:
Level Assignment for Displaying Combinational Logic.
DSD 2001: 148-151 |
| 102 | EE | Bernd Becker,
Thomas Eschbach,
Rolf Drechsler,
Wolfgang Günther:
Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement.
DSD 2001: 54-61 |
| 101 | EE | Migyoung Jung,
Gueesang Lee,
Sungju Park,
Rolf Drechsler:
Minimization of OPKFDDs Using Genetic Algorithms.
DSD 2001: 72-78 |
| 100 | EE | Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Multi-objective Optimisation Based on Relation Favour.
EMO 2001: 154-166 |
| 99 | EE | Nicole Drechsler,
Frank Schmiedle,
Daniel Große,
Rolf Drechsler:
Heuristic Learning Based on Genetic Programming.
EuroGP 2001: 1-10 |
| 98 | EE | Frank Schmiedle,
Daniel Große,
Rolf Drechsler,
Bernd Becker:
Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics.
Fuzzy Days 2001: 479-491 |
| 97 | | Frank Schmiedle,
Wolfgang Günther,
Rolf Drechsler:
Selection of Efficient Re-Ordering Heuristics for MDD Construction.
ISMVL 2001: 299-304 |
| 96 | EE | Wolfgang Günther,
Rolf Drechsler:
Implementation of Read- k-times BDDs on Top of Standard BDD Packages.
VLSI Design 2001: 173-178 |
| 95 | EE | Wolfgang Günther,
Rolf Drechsler:
Performance Driven Optimization for MUX based FPGAs.
VLSI Design 2001: 311-316 |
| 94 | | Peer Johannsen,
Rolf Drechsler:
Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths.
VLSI-SOC 2001: 361-374 |
| 93 | EE | Dragan Jankovic,
Radomir S. Stankovic,
Rolf Drechsler:
Decision Diagram Method for Calculation of Pruned Walsh Transform.
IEEE Trans. Computers 50(2): 147-157 (2001) |
| 92 | EE | Rolf Drechsler,
Wolfgang Günther,
Fabio Somenzi:
Using lower bounds during dynamic BDD minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 51-57 (2001) |
| 91 | EE | Rolf Drechsler,
Wolfgang Günther:
History-based dynamic BDD minimization.
Integration 31(1): 51-63 (2001) |
| 90 | EE | Martin Keim,
Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits.
J. Electronic Testing 17(1): 37-51 (2001) |
| 89 | EE | Rolf Drechsler,
Detlef Sieling:
Binary decision diagrams in theory and practice.
STTT 3(2): 112-136 (2001) |
| 2000 |
|---|
| 88 | EE | Wolfgang Günther,
Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Verification of Designs Containing Black Boxes.
EUROMICRO 2000: 1100-1105 |
| 87 | EE | Wolfgang Günther,
Rolf Drechsler:
ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs.
EUROMICRO 2000: 1130-1137 |
| 86 | EE | Rolf Drechsler,
Wolfgang Günther,
Bernd Becker:
Testability of Circuits Derived from Lattice Diagrams.
EUROMICRO 2000: 1188-1192 |
| 85 | EE | Rolf Drechsler,
Nicole Drechsler,
Elke Mackensen,
Tobias Schubert,
Bernd Becker:
Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System.
EUROMICRO 2000: 1425- |
| 84 | | Wolfgang Günther,
Rolf Drechsler:
Improving EAs for Sequencing Problems.
GECCO 2000: 175-180 |
| 83 | | Tobias Schubert,
Elke Mackensen,
Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Specialized Hardware for Implementation of Evolutionary Algorithms.
GECCO 2000: 369 |
| 82 | | Rolf Drechsler,
Wolfgang Günther:
Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints.
GECCO 2000: 513-518 |
| 81 | EE | Wolfgang Günther,
Rolf Drechsler,
Stefan Höreth:
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation.
ICCD 2000: 383-388 |
| 80 | EE | Per Lindgren,
Rolf Drechsler,
Bernd Becker:
Minimization of Ordered Pseudo Kronecker Decision Diagrams.
ICCD 2000: 504- |
| 79 | EE | Dragan Jankovic,
Wolfgang Günther,
Rolf Drechsler:
Lower Bound Sifting for MDDs.
ISMVL 2000: 193-198 |
| 78 | EE | Frank Schmiedle,
Wolfgang Günther,
Rolf Drechsler:
Dynamic Re-Encoding During MDD Minimization.
ISMVL 2000: 239-244 |
| 77 | EE | Rolf Drechsler,
Mitchell A. Thornton,
David Wessels:
MDD-Based Synthesis of Multi-Valued Logic Networks.
ISMVL 2000: 41-46 |
| 76 | EE | Mitchell A. Thornton,
Rolf Drechsler,
Wolfgang Günther:
A Method for Approximate Equivalence Checking.
ISMVL 2000: 447-452 |
| 75 | EE | Rolf Drechsler,
Mitchell A. Thornton:
Computation of Spectral Information from Logic Netlists.
ISMVL 2000: 53-58 |
| 74 | EE | Rolf Drechsler,
Nicole Drechsler,
Wolfgang Günther:
Fast exact minimization of BDD's.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 384-389 (2000) |
| 73 | EE | Wolfgang Günther,
Rolf Drechsler:
On the computational power of linearly transformed BDDs.
Inf. Process. Lett. 75(3): 119-125 (2000) |
| 72 | EE | Rolf Drechsler,
Bernd Becker,
Nicole Drechsler:
OKFDD minimization by genetic algorithms with application to circuit design.
Integration 28(2): 121-139 (2000) |
| 71 | EE | A. Zuzek,
Rolf Drechsler,
Mitchell A. Thornton:
Boolean function representation and spectral characterization using AND/OR graphs.
Integration 29(2): 101-116 (2000) |
| 1999 |
|---|
| 70 | EE | Yibin Ye,
Kaushik Roy,
Rolf Drechsler:
Power Consumption in XOR-Based Circuits.
ASP-DAC 1999: 299-302 |
| 69 | EE | Rolf Drechsler,
Nicole Drechsler:
Exploiting Don't Caers During Data Sequencing using Genetic Algorithms.
ASP-DAC 1999: 303- |
| 68 | EE | Wolfgang Günther,
Rolf Drechsler:
Minimization of Free BDDs.
ASP-DAC 1999: 323-326 |
| 67 | EE | Rolf Drechsler,
Wolfgang Günther:
Using Lower Bounds During Dynamic BDD Minimization.
DAC 1999: 29-32 |
| 66 | EE | Stefan Höreth,
Rolf Drechsler:
Formal Verification of Word-Level Specifications.
DATE 1999: 52-57 |
| 65 | EE | Mitchell A. Thornton,
J. P. Williams,
Rolf Drechsler,
Nicole Drechsler:
Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities.
DATE 1999: 758-759 |
| 64 | EE | Rolf Drechsler,
Wolfgang Günther:
Generation of Optimal Universal Logic Modules.
EUROMICRO 1999: 1080-1085 |
| 63 | EE | Rolf Drechsler,
Dragan Jankovic,
Radomir S. Stankovic:
Generic Implementation of DD Packages in MVL.
EUROMICRO 1999: 1352-1359 |
| 62 | EE | Rolf Drechsler:
Checking Integrity During Dynamic Reordering in Decision Diagrams.
EUROMICRO 1999: 1360-1367 |
| 61 | | Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes.
Fuzzy Days 1999: 108-117 |
| 60 | | Nicole Drechsler,
Wolfgang Günther,
Rolf Drechsler:
Efficient Graph Coloring by Evolutionary Algorithms.
Fuzzy Days 1999: 30-39 |
| 59 | EE | Wolfgang Günther,
Rolf Drechsler:
Efficient manipulation algorithms for linearly transformed BDDs.
ICCAD 1999: 50-54 |
| 58 | EE | Per Lindgren,
Rolf Drechsler,
Bernd Becker:
Synthesis of Pseudo Kronecker Lattice Diagrams.
ICCD 1999: 307-310 |
| 57 | EE | Wolfgang Günther,
Rolf Drechsler:
Minimization of BDDs using linear transformations based on evolutionary techniques.
ISCAS (1) 1999: 387-390 |
| 56 | EE | Rolf Drechsler,
Marc Herbstritt,
Bernd Becker:
Grouping heuristics for word-level decision diagrams.
ISCAS (1) 1999: 411-414 |
| 55 | EE | Frank Schmiedle,
Rolf Drechsler,
Bernd Becker:
Exact channel routing using symbolic representation.
ISCAS (6) 1999: 394-397 |
| 54 | EE | Franc Brglez,
Rolf Drechsler:
Design of experiments in CAD: context and new data sets for ISCAS'99.
ISCAS (6) 1999: 424-427 |
| 53 | EE | Wolfgang Günther,
Rolf Drechsler:
Creating hard problem instances in logic synthesis using exact minimization.
ISCAS (6) 1999: 436-439 |
| 52 | | Rolf Drechsler,
Wolfgang Günther:
History-Based Dynamic Minimization During BDD Construction.
VLSI 1999: 334-345 |
| 51 | | Rolf Drechsler:
Preudo-Kronecker Expressions for Symmetric Functions.
IEEE Trans. Computers 48(9): 987-990 (1999) |
| 50 | | Rolf Drechsler:
Evolutionary Algorithms for VLSI CAD [book Review].
IEEE Trans. Evolutionary Computation 3(3): 251-253 (1999) |
| 49 | EE | Christoph Scholl,
Dirk Möller,
Paul Molitor,
Rolf Drechsler:
BDD minimization using symmetries.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(2): 81-100 (1999) |
| 48 | EE | Rolf Drechsler,
Harry Hengster,
Horst Schäfer,
Joachim Hartmann,
Bernd Becker:
Testability of 2-Level AND/EXOR Circuits.
J. Electronic Testing 14(3): 219-225 (1999) |
| 1998 |
|---|
| 47 | | Rolf Drechsler,
Stefan Höreth:
Manipulation of *BMDs.
ASP-DAC 1998: 433-438 |
| 46 | | Gueesang Lee,
Rolf Drechsler:
ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions.
ASP-DAC 1998: 75-80 |
| 45 | EE | Rolf Drechsler,
Nicole Drechsler,
Wolfgang Günther:
Fast Exact Minimization of BDDs.
DAC 1998: 200-205 |
| 44 | EE | Stefan Höreth,
Rolf Drechsler:
Dynamic Minimization of Word-Level Decision Diagrams.
DATE 1998: 612-617 |
| 43 | EE | Wolfgang Günther,
Rolf Drechsler:
Linear Transformations and Exact Minimization of BDDs.
Great Lakes Symposium on VLSI 1998: 325-330 |
| 42 | EE | Martin Keim,
Nicole Drechsler,
Rolf Drechsler,
Bernd Becker:
Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm.
ISMVL 1998: 215- |
| 41 | EE | D. Miller,
Rolf Drechsler:
Implementing a Multiple-Valued Decision Diagram Package.
ISMVL 1998: 52-57 |
| 40 | EE | Per Lindgren,
Rolf Drechsler,
Bernd Becker:
Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions.
ISMVL 1998: 95- |
| 39 | EE | Rolf Drechsler:
Verifying Integrity of Decision Diagrams.
SAFECOMP 1998: 380-389 |
| 38 | | Rolf Drechsler,
Bernd Becker,
Andrea Jahnke:
On Variable Ordering and Decomposition Type Choice in OKFDDs.
IEEE Trans. Computers 47(12): 1398-1403 (1998) |
| 37 | EE | Rolf Drechsler,
Bernd Becker:
Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(10): 965-973 (1998) |
| 36 | EE | Rolf Drechsler,
Martin Sauerhoff,
Detlef Sieling:
The complexity of the inclusion operation on OFDD's.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(5): 457-459 (1998) |
| 1997 |
|---|
| 35 | EE | Andreas Hett,
Rolf Drechsler,
Bernd Becker:
Fast and efficient construction of BDDs by reordering based synthesis.
ED&TC 1997: 168-175 |
| 34 | EE | Rolf Drechsler,
Harry Hengster,
Horst Schäfer,
Joachim Hartmann,
Bernd Becker:
Testability of 2-level AND/EXOR circuits.
ED&TC 1997: 548-553 |
| 33 | EE | Christoph Scholl,
Rolf Drechsler,
Bernd Becker:
Functional simulation using binary decision diagrams.
ICCAD 1997: 8-12 |
| 32 | EE | Rolf Drechsler,
Martin Keim,
Bernd Becker:
Fault Simulation in Sequential Multi-Valued Logic Networks.
ISMVL 1997: 145- |
| 31 | EE | Craig M. Files,
Rolf Drechsler,
Marek A. Perkowski:
Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams.
ISMVL 1997: 27- |
| 30 | EE | Radomir S. Stankovic,
Rolf Drechsler:
Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued Functions.
ISMVL 1997: 275-280 |
| 29 | EE | Rolf Drechsler,
Martin Keim,
Bernd Becker:
Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions.
ISMVL 1997: 66- |
| 28 | | Rolf Drechsler,
Bernd Becker,
Stefan Ruppertz:
Manipulation Algorithms for K*BMDs.
TACAS 1997: 4-18 |
| 27 | EE | Bernd Becker,
Rolf Drechsler,
Sudhakar M. Reddy:
(Quasi-) Linear Path Delay Fault Tests for Adders.
VLSI Design 1997: 101-105 |
| 26 | EE | Bernd Becker,
Rolf Drechsler:
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions.
VLSI Design 1997: 46-50 |
| 25 | EE | Rolf Drechsler:
Pseudo Kronecker Expressions for Symmetric Functions.
VLSI Design 1997: 511-513 |
| 24 | EE | Martin Keim,
Michael Martin,
Bernd Becker,
Rolf Drechsler,
Paul Molitor:
Polynomial Formal Verification of Multipliers.
VTS 1997: 150-157 |
| 23 | | Bernd Becker,
Rolf Drechsler,
Michael Theobald:
On the Expressive Power of OKFDDs.
Formal Methods in System Design 11(1): 5-21 (1997) |
| 22 | EE | Rolf Drechsler,
Bernd Becker,
Stefan Ruppertz:
The K*BMD: A Verification Data Structure.
IEEE Design & Test of Computers 14(2): 51-59 (1997) |
| 21 | EE | Rolf Drechsler,
Bernd Becker:
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(1): 1-5 (1997) |
| 1996 |
|---|
| 20 | EE | Harry Hengster,
Rolf Drechsler,
Bernd Becker,
Stefan Eckrich,
Tonja Pfeiffer:
AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth.
Asian Test Symposium 1996: 148- |
| 19 | EE | Rolf Drechsler:
Verification of Multi-Valued Logic Networks.
ISMVL 1996: 10-15 |
| 18 | | Rolf Drechsler,
Nicole Göckel,
Bernd Becker:
Learning Heuristics for OBDD Minimization by Evolutionary Algorithms.
PPSN 1996: 730-739 |
| 17 | | Rolf Drechsler,
Michael Theobald,
Bernd Becker:
Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions.
IEEE Trans. Computers 45(11): 1294-1299 (1996) |
| 1995 |
|---|
| 16 | EE | Rolf Drechsler,
Bernd Becker:
Learning heuristics by genetic algorithms.
ASP-DAC 1995 |
| 15 | | Bernd Becker,
Rolf Drechsler,
Michael Theobald:
OKFDDs versus OBDDs and OFDDs.
ICALP 1995: 475-486 |
| 14 | EE | Rolf Drechsler,
Bernd Becker:
Dynamic minimization of OKFDDs.
ICCD 1995: 602- |
| 13 | EE | Rolf Drechsler,
Rolf Krieger,
Bernd Becker:
Random Pattern Fault Simulation in Multi-Valued Circuits.
ISMVL 1995: 98-103 |
| 12 | | Bernd Becker,
Rolf Drechsler,
Ralph Werchner:
On the Relation Betwen BDDs and FDDs.
LATIN 1995: 72-83 |
| 11 | EE | Harry Hengster,
Rolf Drechsler,
Bernd Becker:
On the application of local circuit transformations with special emphasis on path delay fault testability.
VTS 1995: 387-392 |
| 10 | EE | Bernd Becker,
Rolf Drechsler,
Paul Molitor:
On the generation of area-time optimal testable adders.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1049-1066 (1995) |
| 9 | | Bernd Becker,
Rolf Drechsler,
Ralph Werchner:
On the Relation between BDDs and FDDs.
Inf. Comput. 123(2): 185-197 (1995) |
| 8 | EE | Harry Hengster,
Rolf Drechsler,
Bernd Becker:
On local transformations and path delay fault testability.
J. Electronic Testing 7(3): 173-191 (1995) |
| 1994 |
|---|
| 7 | EE | Rolf Drechsler,
Andisheh Sarabi,
Michael Theobald,
Bernd Becker,
Marek A. Perkowski:
Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams.
DAC 1994: 415-419 |
| 6 | | Bernd Becker,
Rolf Drechsler:
Testability of Circuits Derived from Functional Decision Diagrams.
EDAC-ETC-EUROASIC 1994: 667 |
| 5 | EE | Rolf Drechsler,
Bernd Becker,
Michael Theobald:
Fast OFDD based minimization of fixed polarity Reed-Muller expressions.
EURO-DAC 1994: 2-7 |
| 4 | EE | Rolf Drechsler:
BiTeS: a BDD based test pattern generator for strong robust path delay faults.
EURO-DAC 1994: 322-327 |
| 3 | | Bernd Becker,
Rolf Drechsler:
OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms.
ICCD 1994: 106-110 |
| 2 | | Bernd Becker,
Rolf Drechsler:
Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms.
ISMVL 1994: 65-72 |
| 1 | | Harry Hengster,
Rolf Drechsler,
Bernd Becker:
Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model.
VLSI Design 1994: 123-126 |
