Chris J. Myers

2008
64	EE	Naohiro Hamada, Yuuki Shiga, Hiroshi Saito, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper). ACSD 2008: 50-55
63	EE	Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: Hazard Checking of Timed Asynchronous Circuits Revisited. Fundam. Inform. 88(4): 411-435 (2008)
62	EE	David Walter, Scott Little, Chris J. Myers, Nicholas Seegmiller, Tomohiro Yoneda: Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods. IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2223-2235 (2008)
61	EE	Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: A Conservative Framework for Safety-Failure Checking. IEICE Transactions 91-D(3): 642-654 (2008)
60	EE	Hiroyuki Kuwahara, Chris J. Myers: Production-Passage-Time Approximation: A New Approximation Method to Accelerate the Simulation Process of Enzymatic Reactions. Journal of Computational Biology 15(7): 779-792 (2008)
2007
59	EE	Frédéric Béal, Tomohiro Yoneda, Chris J. Myers: Hazard Checking of Timed Asynchronous Circuits Revisited. ACSD 2007: 51-60
58	EE	David Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda: Symbolic Model Checking of Analog/Mixed-Signal Circuits. ASP-DAC 2007: 316-323
57	EE	Nam-Phuong D. Nguyen, Hiroyuki Kuwahara, Chris J. Myers, James P. Keener: The Design of a Genetic Muller C-Element. ASYNC 2007: 95-104
56	EE	Scott Little, David Walter, Kevin Jones, Chris J. Myers: Analog/Mixed-Signal Circuit Verification Using Models Generated from Simulation Traces. ATVA 2007: 114-128
55	EE	David Walter, Scott Little, Chris J. Myers: Bounded Model Checking of Analog and Mixed-Signal Circuits Using an SMT Solver. ATVA 2007: 66-81
54	EE	Scott Little, Alper Sen, Chris J. Myers: Application of Automated Model Generation Techniques to Analog/Mixed-Signal Circuits. MTV 2007: 109-115
53	EE	Hiroyuki Kuwahara, Chris J. Myers: Production-Passage-Time Approximation: A New Approximation Method to Accelerate the Simulation Process of Enzymatic Reactions. RECOMB 2007: 166-180
52	EE	Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda: Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 592-605 (2007)
51	EE	Tomohiro Yoneda, Chris J. Myers: Synthesis of Timed Circuits Based on Decomposition. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1177-1195 (2007)
50	EE	Hiroshi Saito, Naohiro Hamada, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: Scheduling Methods for Asynchronous Circuits with Bundled-Data Implementations Based on the Approximation of Start Times. IEICE Transactions 90-A(12): 2790-2799 (2007)
2006
49	EE	Tomohiro Yoneda, Chris J. Myers: Effective Contraction of Timed STGs for Decomposition Based Timed Circuit Synthesis. ATVA 2006: 229-244
48		Hiroyuki Kuwahara, Chris J. Myers, Michael S. Samoilov: Abstracted Stochastic Analysis of Type 1 Pili Expression in E.coli. BIOCOMP 2006: 125-134
47	EE	Hiroshi Saito, Nattha Jindapetch, Tomohiro Yoneda, Chris J. Myers, Takashi Nanya: ILP-based Scheduling for Asynchronous Circuits in Bundled-Data Implementation. CIT 2006: 172
46	EE	Scott Little, Nicholas Seegmiller, David Walter, Chris J. Myers, Tomohiro Yoneda: Verification of analog/mixed-signal circuits using labeled hybrid petri nets. ICCAD 2006: 275-282
45	EE	Nathan A. Barker, Chris J. Myers, Hiroyuki Kuwahara: Learning Genetic Regulatory Network Connectivity from Time Series Data. IEA/AIE 2006: 962-971
44	EE	Chris J. Myers, Reid R. Harrison, David Walter, Nicholas Seegmiller, Scott Little: The Case for Analog Circuit Verification. Electr. Notes Theor. Comput. Sci. 153(3): 53-63 (2006)
43	EE	Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of timed circuits with failure-directed abstractions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 403-412 (2006)
42	EE	Hiroyuki Kuwahara, Chris J. Myers, Michael S. Samoilov, Nathan A. Barker, Adam P. Arkin: Automated Abstraction Methodology for Genetic Regulatory Networks. T. Comp. Sys. Biology: 150-175 (2006)
2005
41	EE	Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, Chris J. Myers: High Level Synthesis of Timed Asynchronous Circuits. ASYNC 2005: 178-189
40	EE	Tomoya Kitai, Tomohiro Yoneda, Chris J. Myers: Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation. IEICE Transactions 88-D(11): 2555-2564 (2005)
39	EE	Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers: Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. IEICE Transactions 88-D(7): 1646-1661 (2005)
2004
38	EE	Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers: Synthesis of Speed Independent Circuits Based on Decomposition. ASYNC 2004: 135-145
37	EE	Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. Myers: Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits. ATVA 2004: 339-353
36	EE	Scott Little, David Walter, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda: Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets. ATVA 2004: 426-440
2003
35	EE	Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda: Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. ICCAD 2003: 424-432
34	EE	Hao Zheng, Chris J. Myers, David Walter, Scott Little, Tomohiro Yoneda: Verification of Timed Circuits with Failure Directed Abstractions. ICCD 2003: 28-35
33	EE	Hao Zheng, Eric Mercer, Chris J. Myers: Modular verification of timed circuits using automatic abstraction. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1138-1153 (2003)
2002
32	EE	Tomohiro Yoneda, Tomoya Kitai, Chris J. Myers: Automatic Derivation of Timing Constraints by Failure Analysis. CAV 2002: 195-208
31	EE	Jie Dai, Chris Winstead, Chris J. Myers, Reid R. Harrison, Christian Schlegel: Cell library for automatic synthesis of analog error control decoders. ISCAS (4) 2002: 481-484
30	EE	Tomoya Kitai, Yusuke Oguro, Tomohiro Yoneda, Eric Mercer, Chris J. Myers: Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method. PRDC 2002: 210-220
29	EE	Eric Mercer, Chris J. Myers, Tomohiro Yoneda: Modular Synthesis of Timed Circuits using Partial Order Reduction. Electr. Notes Theor. Comput. Sci. 65(6): (2002)
28	EE	Hans M. Jacobson, Chris J. Myers: Efficient algorithms for exact two-level hazard-free logic minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1269-1283 (2002)
27	EE	Sung Tae Jung, Chris J. Myers: Direct synthesis of timed circuits from free-choice STGs. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 275-290 (2002)
2001
26	EE	Chris Winstead, Jie Dai, Woo Jin Kim, Scott Little, Yong-Bin Kim, Chris J. Myers, Christian Schlegel: Analog MAP Decoder for (8, 4) Hamming Code in Subthreshold CMOS. ARVLSI 2001: 132-147
25	EE	Kip C. Killpack, Eric Mercer, Chris J. Myers: A Standard-Cell Self-Timed Multiplier for Energy and Area Critical Synchronous Systems. ARVLSI 2001: 188-201
24	EE	Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng: Timed circuits: a new paradigm for high-speed design. ASP-DAC 2001: 335-340
23	EE	Chris J. Myers, Hans M. Jacobson: Efficient Exact Two-Level Hazard-Free Logic Minimization. ASYNC 2001: 64-73
22	EE	Bin Zhou, Tomohiro Yoneda, Chris J. Myers: Framework of Timed Trace Theoretic Verification Revisited. Asian Test Symposium 2001: 437-442
21	EE	Hao Zheng, Eric Mercer, Chris J. Myers: Automatic Abstraction for Verification of Timed Circuits and Systems. CAV 2001: 182-193
20	EE	Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Timed circuit verification using TEL structures. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 129-146 (2001)
2000
19		Hans M. Jacobson, Chris J. Myers, Ganesh Gopalakrishnan: Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. ICCAD 2000: 303-310
18	EE	Allen E. Sjogren, Chris J. Myers: Interfacing synchronous and asynchronous modules within a high-speed pipeline. IEEE Trans. VLSI Syst. 8(5): 573-583 (2000)
17	EE	Wendy Belluomini, Chris J. Myers: Timed state space exploration using POSETs. IEEE Trans. on CAD of Integrated Circuits and Systems 19(5): 501-520 (2000)
1999
16	EE	Wendy Belluomini, Chris J. Myers, H. Peter Hofstee: Verification of Delayed-Reset Domino Circuits Using ATACS. ASYNC 1999: 3-12
15	EE	Shai Rotem, Ken S. Stevens, Charles Dike, Marly Roncken, Boris Agapiev, Ran Ginosar, Rakefet Kol, Peter A. Beerel, Chris J. Myers, Kenneth Y. Yun: RAPPID: An Asynchronous Instruction Length Decoder. ASYNC 1999: 60-70
14	EE	Sung Tae Jung, Chris J. Myers: Direct synthesis of timed asynchronous circuits. ICCAD 1999: 332-338
13	EE	Brandon M. Bachman, Hao Zheng, Chris J. Myers: Architectural Synthesis of Timed Asynchronous Systems. ICCD 1999: 354-363
12	EE	Robert Thacker, Wendy Belluomini, Chris J. Myers: Timed Circuit Synthesis Using Implicit Methods. VLSI Design 1999: 181-188
11	EE	Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng: POSET timing and its application to the synthesis and verification of gate-level timed circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 769-786 (1999)
1998
10	EE	Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun: Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. ASYNC 1998: 80-
9		Wendy Belluomini, Chris J. Myers: Verification of Timed Systems Using POSETs. CAV 1998: 403-415
8	EE	Peter A. Beerel, Chris J. Myers, Teresa H. Y. Meng: Covering conditions and algorithms for the synthesis of speed-independent circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 17(3): 205-219 (1998)
1997
7	EE	Allen E. Sjogren, Chris J. Myers: Interfacing Synchronous and Asynchronous Modules Within a High-Speed Pipeline. ARVLSI 1997: 47-61
6	EE	Wendy Belluomini, Chris J. Myers: Efficient Timing Analysis Algorithms for Timed State Space Exploration. ASYNC 1997: 88-100
1995
5	EE	Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng: Automatic synthesis of gate-level timed circuits with choice. ARVLSI 1995: 42-58
4	EE	Chris J. Myers, Peter A. Beerel, Teresa H. Y. Meng: Technology mapping of timed circuits. ASYNC 1995: 138-
1994
3		Tomas Rokicki, Chris J. Myers: Automatic Verification of Timed Circuits. CAV 1994: 468-480
1993
2	EE	Chris J. Myers, Teresa H. Y. Meng: Synthesis of timed asynchronous circuits. IEEE Trans. VLSI Syst. 1(2): 106-119 (1993)
1992
1		Chris J. Myers, Teresa H. Y. Meng: Synthesis of Timed Asynchronous Circuits. ICCD 1992: 279-284

Coauthor Index

1	Boris Agapiev	[15]
2	Adam P. Arkin	[42]
3	Brandon M. Bachman	[13]
4	Nathan A. Barker	[42] [45]
5	Frédéric Béal	[59] [61] [63]
6	Peter A. Beerel	[4] [8] [10] [15]
7	Wendy Belluomini	[6] [9] [12] [16] [17] [20] [24]
8	Wei-Chun Chou	[10]
9	Jie Dai	[26] [31]
10	Charles Dike	[15]
11	Ran Ginosar	[10] [15]
12	Ganesh Gopalakrishnan	[19]
13	Naohiro Hamada	[50] [64]
14	Reid R. Harrison	[31] [44]
15	H. Peter Hofstee	[16] [20]
16	Hans M. Jacobson	[19] [23] [28]
17	Nattha Jindapetch	[47] [50]
18	Kevin Jones	[56]
19	Sung Tae Jung	[14] [27]
20	Kip Kallpack	[24]
21	Manabu Kato	[41]
22	James P. Keener	[57]
23	Kip C. Killpack	[25]
24	Woo Jin Kim	[26]
25	Yong-Bin Kim	[26]
26	Tomoya Kitai	[30] [32] [40]
27	Rakefet Kol	[10] [15]
28	Hiroyuki Kuwahara	[42] [45] [48] [53] [57] [60]
29	Scott Little	[26] [34] [36] [43] [44] [46] [54] [55] [56] [58] [62]
30	Atsushi Matsumoto	[41]
31	Teresa H. Y. Meng	[1] [2] [4] [5] [8] [11]
32	Eric Mercer (Eric G. Mercer)	[21] [25] [29] [30] [33]
33	Takashi Nanya	[47] [50] [64]
34	Curtis A. Nelson	[35] [52]
35	Nam-Phuong D. Nguyen	[57]
36	Yusuke Oguro	[30]
37	Hiroomi Onda	[38]
38	Eric Peskin	[24]
39	Denduang Pradubsuwun	[37] [39]
40	Tomas Rokicki	[3] [5] [11]
41	Marly Roncken	[15]
42	Shai Rotem	[10] [15]
43	Hiroshi Saito	[47] [50] [64]
44	Michael S. Samoilov	[42] [48]
45	Christian Schlegel	[26] [31]
46	Nicholas Seegmiller	[36] [44] [46] [58] [62]
47	Alper Sen	[54]
48	Yuuki Shiga	[64]
49	Allen E. Sjogren	[7] [18]
50	Ken S. Stevens	[10] [15]
51	Robert Thacker	[12]
52	David Walter	[34] [36] [43] [44] [46] [55] [56] [58] [62]
53	Chris Winstead	[26] [31]
54	Tomohiro Yoneda	[22] [29] [30] [32] [34] [35] [36] [37] [38] [39] [40] [41] [43] [46] [47] [49] [50] [51] [52] [58] [59] [61] [62] [63] [64]
55	Kenneth Y. Yun	[10] [15]
56	Hao Zheng	[13] [21] [24] [33] [34] [43]
57	Bin Zhou	[22]

Colors in the list of coauthors