| 2009 |
|---|
| 13 | EE | Jason Helge Anderson:
Emerging application domains: research challenges and opportunities for FPGAs.
FPGA 2009: 1-2 |
| 12 | EE | Qiang Wang,
Subodh Gupta,
Jason Helge Anderson:
Clock power reduction for virtex-5 FPGAs.
FPGA 2009: 13-22 |
| 2008 |
|---|
| 11 | EE | Taneem Ahmed,
Paul D. Kundarewich,
Jason Helge Anderson,
Brad L. Taylor,
Rajat Aggarwal:
Architecture-specific packing for virtex-5 FPGAs.
FPGA 2008: 5-13 |
| 2006 |
|---|
| 10 | EE | Jason Helge Anderson,
Farid N. Najm:
Active leakage power optimization for FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 423-437 (2006) |
| 2004 |
|---|
| 9 | EE | Jason Helge Anderson,
Farid N. Najm:
Interconnect capacitance estimation for FPGAs.
ASP-DAC 2004: 713-718 |
| 8 | EE | Jason Helge Anderson,
Farid N. Najm,
Tim Tuan:
Active leakage power optimization for FPGAs.
FPGA 2004: 33-41 |
| 7 | EE | Jason Helge Anderson,
Sudip Nag,
Kamal Chaudhary,
Sandor Kalman,
Chari Madabhushi,
Paul Cheng:
Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis.
FPL 2004: 168-178 |
| 6 | EE | Jason Helge Anderson,
Farid N. Najm:
Low-power programmable routing circuitry for FPGAs.
ICCAD 2004: 602-609 |
| 5 | EE | Jason Helge Anderson,
Farid N. Najm:
Power estimation techniques for FPGAs.
IEEE Trans. VLSI Syst. 12(10): 1015-1027 (2004) |
| 2003 |
|---|
| 4 | EE | Jason Helge Anderson,
Farid N. Najm:
Switching activity analysis and pre-layout activity prediction for FPGAs.
SLIP 2003: 15-21 |
| 2000 |
|---|
| 3 | EE | Jason Helge Anderson,
Jim Saunders,
Sudip Nag,
Chari Madabhushi,
Rajeev Jayaraman:
A Placement Algorithm for FPGA Designs with Multiple I/O Standards.
FPL 2000: 211-220 |
| 1998 |
|---|
| 2 | EE | Jason Helge Anderson,
Stephen Dean Brown:
Technology Mapping for Large Complex PLDs.
DAC 1998: 698-703 |
| 1 | EE | Jason Helge Anderson,
Stephen Dean Brown:
An LPGA with Foldable PLA-style Logic Blocks.
FPGA 1998: 244-252 |
