| 2006 |
|---|
| 11 | EE | Jason Cong,
Michail Romesis,
Joseph R. Shinnerl:
Fast floorplanning by look-ahead enabled recursive bipartitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1719-1732 (2006) |
| 2005 |
|---|
| 10 | EE | Jason Cong,
Michail Romesis,
Joseph R. Shinnerl:
Fast floorplanning by look-ahead enabled recursive bipartitioning.
ASP-DAC 2005: 1119-1122 |
| 9 | EE | Ashok Jagannathan,
Hannah Honghua Yang,
Kris Konigsfeld,
Dan Milliron,
Mosur Mohan,
Michail Romesis,
Glenn Reinman,
Jason Cong:
Microarchitecture evaluation with floorplanning and interconnect pipelining.
ASP-DAC 2005: 8-15 |
| 8 | | Jason Cong,
Michail Romesis,
Joseph R. Shinnerl:
Robust mixed-size placement under tight white-space constraints.
ICCAD 2005: 165-172 |
| 7 | EE | Tony F. Chan,
Jason Cong,
Michail Romesis,
Joseph R. Shinnerl,
Kenton Sze,
Min Xie:
mPL6: a robust multilevel mixed-size placement engine.
ISPD 2005: 227-229 |
| 2004 |
|---|
| 6 | EE | Jason Cong,
Gabriele Nataneli,
Michail Romesis,
Joseph R. Shinnerl:
An area-optimality study of floorplanning.
ISPD 2004: 78-83 |
| 5 | EE | Chin-Chih Chang,
Jason Cong,
Michail Romesis,
Min Xie:
Optimality and scalability study of existing placement algorithms.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 537-549 (2004) |
| 2003 |
|---|
| 4 | EE | Jason Cong,
Ashok Jagannathan,
Glenn Reinman,
Michail Romesis:
Microarchitecture evaluation with physical planning.
DAC 2003: 32-35 |
| 3 | EE | Jason Cong,
Michail Romesis,
Min Xie:
Optimality and Stability Study of Timing-Driven Placement Algorithms.
ICCAD 2003: 472-479 |
| 2 | EE | Jason Cong,
Michail Romesis,
Min Xie:
Optimality, scalability and stability study of partitioning and placement algorithms.
ISPD 2003: 88-94 |
| 2001 |
|---|
| 1 | EE | Jason Cong,
Michail Romesis:
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping.
DAC 2001: 389-394 |
