Indradeep Ghosh

2008
33	EE	Xin Li, Daryl Shannon, Indradeep Ghosh, Mizuhito Ogawa, Sreeranga P. Rajan, Sarfraz Khurshid: Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution. APLAS 2008: 36-52
2006
32	EE	Indradeep Ghosh, Mukul R. Prasad: A Technique for Estimating the Difficulty of a Formal Verification Problem. ISQED 2006: 63-70
31	EE	Liang Zhang, Indradeep Ghosh, Michael S. Hsiao: A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2526-2538 (2006)
2005
30	EE	Indradeep Ghosh: High Level Test Generation for Custom Hardware: An Industrial Perspective. Asian Test Symposium 2005: 458
2004
29	EE	Indradeep Ghosh, Rajarshi Mukherjee, Mukul R. Prasad, Masahiro Fujita: High Level Design Validation: Current Practices and Future Directions. VLSI Design 2004: 9-11
2003
28	EE	Indradeep Ghosh, Srivaths Ravi: On automatic generation of RTL validation test benches using circuit testing techniques. ACM Great Lakes Symposium on VLSI 2003: 289-294
27	EE	Liang Zhang, Michael S. Hsiao, Indradeep Ghosh: Automatic Design Validation Framework for HDL Descriptions via RTL ATPG. Asian Test Symposium 2003: 148-153
26	EE	Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh: Precomputation-based Guarding for Dynamic and Leakage Power Reduction. ICCD 2003: 90-97
25	EE	Liang Zhang, Indradeep Ghosh, Michael S. Hsiao: Efficient Sequential ATPG for Functional RTL Circuits. ITC 2003: 290-298
2002
24	EE	Indradeep Ghosh, Krishna Sekar, Vamsi Boppana: Design for Verification at the Register Transfer Level. VLSI Design 2002: 420-425
2001
23	EE	Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha: Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. IEEE Trans. on CAD of Integrated Circuits and Systems 20(12): 1414-1425 (2001)
22	EE	Indradeep Ghosh, Masahiro Fujita: Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 20(3): 402-415 (2001)
2000
21	EE	Indradeep Ghosh, Masahiro Fujita: Automatic test pattern generation for functional RTL circuits using assignment decision diagrams. DAC 2000: 43-48
20	EE	Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana: A Technique for Identifying RTL and Gate-Level Correspondences. ICCD 2000: 591-
19	EE	Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita: Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design 2000: 436-441
18	EE	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik: A BIST scheme for RTL circuits based on symbolic testabilityanalysis. IEEE Trans. on CAD of Integrated Circuits and Systems 19(1): 111-128 (2000)
17	EE	Indradeep Ghosh, Sujit Dey, Niraj K. Jha: A fast and low-cost testing technique for core-based system-chips. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 863-877 (2000)
1999
16	EE	Indradeep Ghosh, Niraj K. Jha, Sujit Dey: A low overhead design for testability and test generation technique for core-based systems-on-a-chip. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1661-1676 (1999)
15	EE	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Hierarchical test generation and design for testability methods for ASPPs and ASIPs. IEEE Trans. on CAD of Integrated Circuits and Systems 18(3): 357-370 (1999)
1998
14	EE	Indradeep Ghosh, Sujit Dey, Niraj K. Jha: A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. DAC 1998: 542-547
13	EE	Indradeep Ghosh, Niraj K. Jha, Sudipta Bhawmik: A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. DAC 1998: 554-559
12	EE	Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey: Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. VLSI Design 1998: 193-198
11	EE	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: A design-for-testability technique for register-transfer level circuits using control/data flow extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 706-723 (1998)
10	EE	Indradeep Ghosh, Niraj K. Jha: High-level test synthesis: a survey. Integration 26(1-2): 79-99 (1998)
9	EE	Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey: Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. J. Electronic Testing 13(2): 201-212 (1998)
1997
8	EE	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Hierarchical Test Generation and Design for Testability of ASPPs and ASIPs. DAC 1997: 534-539
7		Indradeep Ghosh, Niraj K. Jha, Sujit Dey: A Low-Overhead Design for Testability and Test Generation Technique for Core-Based Systems. ITC 1997: 50-59
6	EE	Sudipta Bhawmik, Indradeep Ghosh: A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. VLSI Design 1997: 284-288
5	EE	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 16(9): 1001-1014 (1997)
1996
4	EE	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: A design for testability technique for RTL circuits using control/data flow extraction. ICCAD 1996: 329-336
1995
3	EE	Indradeep Ghosh, Anand Raghunathan, Niraj K. Jha: Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. ICCD 1995: 173-179
2		Indradeep Ghosh, Bandana Majumdar: VLSI Implementation of An Efficient ASIC Architecture for Real-Time Rotation of Digital Images. IJPRAI 9(2): 449-462 (1995)
1994
1		Indradeep Ghosh, Bandana Majumdar: Design of an Application Specific VLSI Chip for Image Rotation. VLSI Design 1994: 275-278

Coauthor Index

1	Afshin Abdollahi	[26]
2	Sudipta Bhawmik	[6] [13] [18]
3	Vamsi Boppana	[19] [20] [23] [24]
4	Sujit Dey	[7] [9] [12] [14] [16] [17]
5	Farzan Fallah	[26]
6	Masahiro Fujita	[19] [21] [22] [29]
7	Michael S. Hsiao	[25] [27] [31]
8	Jawahar Jain	[19]
9	Niraj K. Jha	[3] [4] [5] [7] [8] [10] [11] [13] [14] [15] [16] [17] [18] [20] [23]
10	Sarfraz Khurshid	[33]
11	Xin Li	[33]
12	Bandana Majumdar	[1] [2]
13	Rajarshi Mukherjee	[19] [29]
14	Mizuhito Ogawa	[33]
15	Massoud Pedram	[26]
16	Mukul R. Prasad	[29] [32]
17	Anand Raghunathan	[3] [4] [5] [8] [11] [15]
18	Sreeranga P. Rajan	[33]
19	Srivaths Ravi	[9] [12] [20] [23] [28]
20	Rabindra K. Roy	[9] [12]
21	Krishna Sekar	[24]
22	Daryl Shannon	[33]
23	Liang Zhang	[25] [27] [31]

Colors in the list of coauthors