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Costas E. Goutis
List of publications from the DBLP Bibliography Server - FAQ
2009 | ||
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91 | EE | Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis: Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays. The Journal of Supercomputing 48(2): 115-151 (2009) |
2008 | ||
90 | EE | Michalis D. Galanis, Costas E. Goutis: Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-path. Journal of Systems Architecture - Embedded Systems Design 54(5): 479-490 (2008) |
89 | EE | Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis: Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path. Signal Processing Systems 50(2): 179-200 (2008) |
2007 | ||
88 | EE | Grigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis: Compiler assisted architectural exploration for coarse grained reconfigurable arrays. ACM Great Lakes Symposium on VLSI 2007: 164-167 |
87 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis: Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-path. ACM Great Lakes Symposium on VLSI 2007: 2-7 |
86 | EE | Grigoris Dimitroulakos, Michalis D. Galanis, Nikos Kostaras, Costas E. Goutis: A unified evaluation framework for coarse grained reconfigurable array architectures. Conf. Computing Frontiers 2007: 161-172 |
85 | EE | Athanasios Milidonis, N. Alachiotis, V. Porpodas, Haralambos Michail, Athanasios Kakarountas, Constantinos E. Goutis: Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy. DATE 2007: 612-617 |
84 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis: Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-Path. IPDPS 2007: 1-8 |
83 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis: Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform. PATMOS 2007: 352-362 |
82 | EE | Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis: Speedups in embedded systems with a high-performance coprocessor datapath. ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
81 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms CoRR abs/0710.4844: (2007) |
80 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis: Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System. IEEE Trans. VLSI Syst. 15(12): 1362-1366 (2007) |
79 | EE | Harris E. Michail, George A. Panagiotakopoulos, Vasilis N. Thanasoulis, Athanasios Kakarountas, Costas E. Goutis: Server side hashing core exceeding 3 Gbps of throughput. IJSN 2(3/4): 228-238 (2007) |
78 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: Automated framework for partitioning DSP applications in hybrid reconfigurable platforms. Microprocessors and Microsystems 31(1): 1-14 (2007) |
77 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis: Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-path. The Journal of Supercomputing 39(3): 251-271 (2007) |
76 | EE | Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis: Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture. The Journal of Supercomputing 40(2): 127-157 (2007) |
2006 | ||
75 | EE | Michalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis: Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-Path. ICSAMOS 2006: 85-92 |
74 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis: Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic. IPDPS 2006 |
73 | EE | Grigoris Dimitroulakos, Michalis D. Galanis, Constantinos E. Goutis: Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures. IPDPS 2006 |
72 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis: Mapping DSP applications on processor systems with coarse-grain reconfigurable hardware. IPDPS 2006 |
71 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis: Mapping DSP applications on processor/coarse-grain reconfigurable array architectures. ISCAS 2006 |
70 | EE | Grigoris Dimitroulakos, Michalis D. Galanis, Constantinos E. Goutis: Resource constrained modulo scheduling for coarse-grained reconfigurable arrays. ISCAS 2006 |
69 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis: A high-performance data path for synthesizing DSP kernels. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1154-1162 (2006) |
68 | EE | Michalis D. Galanis, Athanasios Milidonis, Athanasios Kakarountas, Costas E. Goutis: A design flow for speeding-up dsp applications in heterogeneous reconfigurable systems. Microelectronics Journal 37(6): 554-564 (2006) |
67 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis: Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCs. The Journal of Supercomputing 35(2): 185-199 (2006) |
66 | EE | Athanasios Kakarountas, Haralambos Michail, Athanasios Milidonis, Costas E. Goutis, George Theodoridis: High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications. The Journal of Supercomputing 37(2): 179-195 (2006) |
65 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis: Partitioning Methodology for Heterogeneous Reconfigurable Functional Units. The Journal of Supercomputing 38(1): 17-34 (2006) |
2005 | ||
64 | EE | Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis: Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays. ASAP 2005: 161-168 |
63 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis: Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware. ASAP 2005: 50-59 |
62 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis: Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid Systems. FCCM 2005: 301-302 |
61 | Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis: Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs. FPL 2005: 630-635 | |
60 | EE | Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis: A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable Architectures. IPDPS 2005 |
59 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms. IPDPS 2005 |
58 | EE | Grigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis, Athanasios Milidonis: A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standard. ISCAS (1) 2005: 472-475 |
57 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: A methodology for partitioning DSP applications in hybrid reconfigurable systems. ISCAS (2) 2005: 1206-1209 |
56 | EE | Michalis D. Galanis, Gregory Dimitroulakos, Constantinos E. Goutis: An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arrays. ISCAS (4) 2005: 3519-3522 |
55 | EE | Haralambos Michail, A. P. Kakarountas, Odysseas G. Koufopavlou, Constantinos E. Goutis: A low-power and high-throughput implementation of the SHA-1 hash function. ISCAS (4) 2005: 4086-4089 |
54 | EE | Michalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis: Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCs. PATMOS 2005: 247-256 |
53 | EE | Haralambos Michail, Athanasios Kakarountas, George N. Selimis, Costas E. Goutis: Optimizing SHA-1 Hash Function for High Throughput with a Partial Unrolling Study. PATMOS 2005: 591-600 |
52 | EE | Michalis D. Galanis, Paris Kitsos, Giorgos Kostopoulos, Nicolas Sklavos, Constantinos E. Goutis: Comparison of the Hardware Implementation of Stream Ciphers. Int. Arab J. Inf. Technol. 2(4): 267-274 (2005) |
51 | EE | Grigoris Dimitroulakos, Michalis D. Galanis, Athanasios Milidonis, Constantinos E. Goutis: A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000. Integration 39(1): 1-11 (2005) |
50 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis: A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. Journal of Circuits, Systems, and Computers 14(4): 877-893 (2005) |
2004 | ||
49 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. DATE 2004: 247-252 |
48 | EE | Michalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms. DATE 2004: 247-252 |
47 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis: Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. FCCM 2004: 275-276 |
46 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis: A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. FPGA 2004: 252 |
45 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis: Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. FPL 2004: 868-873 |
44 | EE | Athanasios Kakarountas, Vassilis Spiliotopoulos, Spiridon Nikolaidis, Constantinos E. Goutis: The Impact of Low-Power Techniques on the Design of Portable Safety-Critical Systems. PATMOS 2004: 501-509 |
43 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis: Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. PATMOS 2004: 652-661 |
42 | EE | Dimitris Karatasos, Athanasios Kakarountas, George Theodoridis, Constantinos E. Goutis: A Novel Constant-Time Fault-Secure Binary Counter. PATMOS 2004: 742-749 |
41 | EE | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis: A Novel Data-Path for Accelerating DSP Kernels. SAMOS 2004: 363-372 |
40 | EE | Athanasios Milidonis, Grigoris Dimitroulakos, Michalis D. Galanis, George Theodoridis, Constantinos E. Goutis, Francky Catthoor: An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications. SCOPES 2004: 122-136 |
39 | EE | Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man: Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors. VLSI Signal Processing 37(1): 53-73 (2004) |
2003 | ||
38 | EE | Kostas Masselos, Panagiotis Merakos, S. Theoharis, Thanos Stouraitis, Constantinos E. Goutis: Power efficient data path synthesis of sum-of-products computations. IEEE Trans. VLSI Syst. 11(3): 446-450 (2003) |
37 | EE | Spiridon Nikolaidis, E. Karaolis, Athanasios Kakarountas, K. Papadomanolakis, Constantinos E. Goutis: A Methodology for Calculating the Undetectable Double-Faults in Self-Checking Circuits. Journal of Circuits, Systems, and Computers 12(1): 75-92 (2003) |
2002 | ||
36 | EE | Nikolaos D. Liveris, Nikolaos D. Zervas, Dimitrios Soudris, Constantinos E. Goutis: A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications. DATE 2002: 977-983 |
35 | EE | Athanasios Kakarountas, K. Papadomanolakis, Spiridon Nikolaidis, Dimitrios Soudris, Constantinos E. Goutis: Confronting violations of the TSCG(T) in low-power design. ISCAS (4) 2002: 313-316 |
34 | EE | Kostas Masselos, Panagiotis Merakos, Constantinos E. Goutis: Power Efficient Vector Quantization Design Using Pixel Truncation. PATMOS 2002: 409-418 |
33 | EE | Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man: A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors. IEEE Trans. VLSI Syst. 10(4): 515-518 (2002) |
32 | EE | S. Theoharis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis, Adonios Thanailakis: A fast and accurate delay dependent method for switching estimation of large combinational circuits. Journal of Systems Architecture 48(4-5): 113-124 (2002) |
2001 | ||
31 | EE | Yiannis Andreopoulos, Nikolaos D. Zervas, Gauthier Lafruit, Peter Schelkens, Thanos Stouraitis, Costas E. Goutis, Jan Cornelis: A local wavelet transform implementation versus an optimal row-column algorithm for the 2D multilevel decomposition. ICIP (3) 2001: 330-333 |
30 | EE | Nikolas Kroupis, Minas Dasygenis, Antonios Argyriou, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis, Nikolaos D. Zervas, Constantinos E. Goutis: Power, performance and area exploration of block matching algorithms mapped on programmable processors. ICIP (3) 2001: 728-731 |
29 | EE | Nikolaos D. Zervas, I. Tagopoulos, Vassilis Spiliotopoulos, Giorgos P. Anagnostopoulos, Dimitrios Soudris, Constantinos E. Goutis: Performance comparison of DWT scheduling alternatives on programmable platforms. ISCAS (2) 2001: 761-764 |
28 | Nikolaos D. Zervas, Giorgos P. Anagnostopoulos, Vassilis Spiliotopoulos, Yiannis Andreopoulos, Costas E. Goutis: Evaluation of design alternatives for the 2-D-discrete wavelet transform. IEEE Trans. Circuits Syst. Video Techn. 11(12): 1246-1262 (2001) | |
2000 | ||
27 | EE | Kostas Masselos, S. Theoharis, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis: Low power synthesis of sum-of-products computation (poster session). ISLPED 2000: 234-237 |
26 | EE | Athanasios Kakarountas, K. Papadomanolakis, V. Kokkinos, Constantinos E. Goutis: Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance. PATMOS 2000: 187-194 |
25 | EE | Dimitrios Soudris, Nikolaos D. Zervas, Antonios Argyriou, Minas Dasygenis, Konstantinos Tatas, Constantinos E. Goutis, Adonios Thanailakis: Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications. PATMOS 2000: 243-254 |
24 | EE | Nikolaos D. Zervas, S. Theoharis, Athanasios Kakarountas, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis: Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers. PATMOS 2000: 47-55 |
23 | EE | George Theodoridis, S. Theoharis, Nikolaos D. Zervas, Constantinos E. Goutis: Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions. PATMOS 2000: 76-87 |
22 | EE | Kostas Masselos, Koen Danckaert, Francky Catthoor, Nikolaos D. Zervas, Constantinos E. Goutis, Hugo De Man: A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints. VLSI Signal Processing 26(3): 291-317 (2000) |
1999 | ||
21 | EE | M. Perakis, A. E. Tzimas, E. G. Metaxakis, Dimitrios Soudris, G. A. Kalivas, C. Katis, Chrissavgi Dre, Constantinos E. Goutis, Adonios Thanailakis, Thanos Stouraitis: The VLSI implementation of a baseband receiver for DECT-based portable applications. ISCAS (1) 1999: 198-201 |
20 | EE | George Theodoridis, S. Theoharis, Dimitrios Soudris, Thanos Stouraitis, Constantinos E. Goutis: An efficient probabilistic method for logic circuits using real delay gate model. ISCAS (1) 1999: 286-289 |
19 | EE | Nikolaos D. Zervas, Kostas Masselos, Odysseas G. Koufopavlou, Constantinos E. Goutis: Power exploration of multimedia applications realized on embedded cores. ISCAS (4) 1999: 378-381 |
18 | EE | Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis: Low power synthesis of sum-of-product computation in DSP algorithms. ISCAS (6) 1999: 420-423 |
17 | EE | Kostas Masselos, Koen Danckaert, Francky Catthoor, Constantinos E. Goutis, Hugo De Man: A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints. ISLPED 1999: 270-272 |
16 | EE | Koen Danckaert, Kostas Masselos, Francky Catthoor, Hugo De Man, Constantinos E. Goutis: Strategy for power-efficient design of parallel systems. IEEE Trans. VLSI Syst. 7(2): 258-265 (1999) |
15 | EE | Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis: Novel techniques for bus power consumption reduction in realizations of sum-of-product computation. IEEE Trans. VLSI Syst. 7(4): 492-497 (1999) |
14 | EE | Efstathios D. Kyriakis-Bitzaros, Constantinos E. Goutis: A Space-Time Representation Method of Iterative Algorithms for the Design of Processor Arrays. VLSI Signal Processing 22(3): 151-162 (1999) |
1998 | ||
13 | EE | Labros Bisdounis, Odysseas G. Koufopavlou, Constantinos E. Goutis, Spiridon Nikolaidis: Switching Response Modeling of the CMOS Inverter for Sub-micron Devices. DATE 1998: 729- |
12 | EE | Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis: Trade-Off Analysis of a Low-Power Image Coding Algorithm. VLSI Signal Processing 18(1): 65-80 (1998) |
1995 | ||
11 | Chrissavgi Dre, Anna Tatsaki, Thanos Stouraitis, Constantinos E. Goutis: Alternative Architectures for the 2-D DCT Algorithm. ISCAS 1995: 2156-2159 | |
10 | EE | D. E. Metafas, Constantinos E. Goutis: A floating-point advanced cordic processor. VLSI Signal Processing 10(1): 53-65 (1995) |
1994 | ||
9 | John Ant. Hallas, Evaggelinos P. Mariatos, Michael K. Birbas, Alexios N. Birbas, Constantinos E. Goutis: A CAD Tool for the Development of an Extra-Fast Fuzzy Logic Controller Based on FPGAs and Memory Modules. FPL 1994: 309-311 | |
8 | John Ant. Hallas, Michael K. Birbas, Alexios N. Birbas, John C. Kikidis, Constantinos E. Goutis: Near-Lossless Compression of Continuous-Tone Still Images Using Fuzzy Logic Notions and the Binary Arithmetic Coder (Q-Coder). ISCAS 1994: 125-128 | |
7 | Evaggelinos P. Mariatos, D. E. Metafas, John Ant. Hallas, Constantinos E. Goutis: A Fast DCT Processor, Based on Special Purpose CORDIC Rotators. ISCAS 1994: 271-274 | |
1993 | ||
6 | Efstathios D. Kyriakis-Bitzaros, Odysseas G. Koufopavlou, Constantinos E. Goutis: Space-Time Representation of Iterative Algorithms and The Design of Regular Processor Arrays. ICPP 1993: 2-9 | |
5 | Dimitrios Soudris, P. D. Georgakopoulos, Constantinos E. Goutis: A Systematic Methodology for Designing Multilevel Systolic Architectures. ISCAS 1993: 1738-1741 | |
4 | Spiridon Nikolaidis, D. E. Metafas, Constantinos E. Goutis: CORDIC Based Pipeline Architecture for All-pass Filters. ISCAS 1993: 1917-1920 | |
1992 | ||
3 | EE | Odysseas G. Koufopavlou, Constantinos E. Goutis: Image reconstruction on a special purpose array processor. Image Vision Comput. 10(7): 479-484 (1992) |
2 | Efstathios D. Kyriakis-Bitzaros, Constantinos E. Goutis: An Efficient Decompostion Technique for Mapping Nested Loops with Constant Dependencies into Regular Processor Arrays. J. Parallel Distrib. Comput. 16(3): 258-264 (1992) | |
1991 | ||
1 | Dimitrios Soudris, Michael K. Birbas, Constantinos E. Goutis: Direct mapping of nested loops on piecewise regular processor arrays. Algorithms and Parallel VLSI Architectures 1991: 145-150 |