2008 |
11 | EE | N. Venkateswaran,
V. K. Elangovan,
K. Ganesan,
T. R. S. Sagar,
S. Aananthakrishanan,
S. Ramalingam,
S. Gopalakrishnan,
M. Manivannan,
D. Srinivasan,
V. Krishnamurthy,
K. Chandrasekar,
V. Venkatesan,
B. Subramaniam,
V. Sangkar,
A. Vasudevan,
S. Ganapathy,
S. Murali,
M. Thyagarajan:
On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system.
IPDPS 2008: 1-8 |
2007 |
10 | EE | S. Rahul,
J. Vignesh,
S. Santhosh Kumar,
M. Bharadwaj,
N. Venkateswaran:
Comparison of Pyramidal and Packet Wavelet Coder for Image Compression Using Cellular Neural Network (CNN) with Thresholding and Quantization.
ITNG 2007: 183-184 |
2006 |
9 | EE | N. Venkateswaran,
J. Vignesh,
S. Santhosh Kumar,
S. Rahul,
M. Bharadwaj:
A Frequency Adaptive Packet Wavelet Coder for Still Images Using CNN.
ICHIT 2006: 240-248 |
8 | EE | Chandramouli Visweswariah,
K. Ravindran,
K. Kalafala,
Steven G. Walker,
S. Narayan,
Daniel K. Beece,
J. Piaget,
N. Venkateswaran,
Jeffrey G. Hemmett:
First-Order Incremental Block-Based Statistical Timing Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2170-2180 (2006) |
2005 |
7 | EE | N. Venkateswaran,
S. Balaji,
V. Sridhar:
Fault tolerant bus architecture for deep submicron based processors.
SIGARCH Computer Architecture News 33(1): 148-155 (2005) |
2004 |
6 | EE | N. Venkateswaran,
Krishna Bharath:
Frequency Domain Testing of General Purpose Processors at the Instruction Execution Level.
DELTA 2004: 15-22 |
5 | EE | N. Venkateswaran,
V. Barath Kumar,
R. Raghavan,
R. Srinivas,
S. Subramanian,
V. Balaji,
Venkataraman Mahalingam,
T. L. Rajaprabhu:
Crosstalk Fault Tolerant Processor Architecture - A Power Aware Design.
DELTA 2004: 333-340 |
2003 |
4 | EE | N. Venkateswaran,
C. Chandramouli:
General Purpose Processor Architecture for Modeling Stochastic Biological Neuronal Assemblies.
ICES 2003: 387-397 |
3 | EE | N. Venkateswaran,
V. Balaji,
Venkataraman Mahalingam,
T. L. Rajaprabhu:
Analysis of Bit Transition Count for EDAC Encoded FSM.
IOLTS 2003: 166 |
1995 |
2 | | N. Venkateswaran,
S. Pattabiraman,
R. Devanathan,
B. Kumaran,
Ashraf Ahmed,
Sankara Narayanan,
Radharamanan:
A Design Methodology for Very Large Array Processors - Part 1: Gipop Processor Array.
IJPRAI 9(2): 231-262 (1995) |
1 | | N. Venkateswaran,
S. Pattabiraman,
J. Desouza,
G. Sriram,
R. Srinivasan,
R. Sankar,
G. Suresh:
A Design Methodology for Very Large Array Processors - Part 2: Pacube VLSI Arrays.
IJPRAI 9(2): 263-301 (1995) |