Zhenyu Qi

2009
18	EE	Adam C. Cabe, Zhenyu Qi, Stuart N. Wooters, Travis N. Blalock, Mircea R. Stan: Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay. ISQED 2009: 1-6
2008
17	EE	Zhenyu Qi, Mircea R. Stan: NBTI resilient circuits using adaptive body biasing. ACM Great Lakes Symposium on VLSI 2008: 285-290
2007
16	EE	Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan: Structured and tuned array generation (STAG) for high-performance random logic. ACM Great Lakes Symposium on VLSI 2007: 257-262
15	EE	Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan: Multi-Dimensional Circuit and Micro-Architecture Level Optimization. ISQED 2007: 275-280
14	EE	Zhenyu Qi, Jing Xu: Automatic Performance Evaluation Of Palm Recognition. SNPD (1) 2007: 688-693
2006
13	EE	Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2402-2412 (2006)
12	EE	Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He: Wideband passive multiport model order reduction and realization of RLCM circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1496-1509 (2006)
2005
11	EE	Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan: A wideband hierarchical circuit reduction for massively coupled interconnects. ASP-DAC 2005: 111-114
10	EE	Zhenyu Qi, Sheldon X.-D. Tan, Hao Yu, Lei He: Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction. ASP-DAC 2005: 224-229
9	EE	Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Partitioning-based approach to fast on-chip decap budgeting and minimization. DAC 2005: 170-175
8		Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang: Fast thermal simulation for architecture level dynamic thermal management. ICCAD 2005: 639-644
7		Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He: An efficient method for terminal reduction of interconnect circuits considering delay variations. ICCAD 2005: 821-826
6	EE	Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang: Efficient Thermal Simulation for Run-Time Temperature Tracking and Management. ICCD 2005: 130-136
5	EE	Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong: Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. ISQED 2005: 542-547
4	EE	Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan: Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits. ISQED 2005: 603-608
3	EE	Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi: Hierarchical approach to exact symbolic analysis of large analog circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(8): 1241-1250 (2005)
2004
2	EE	Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi: Hierarchical approach to exact symbolic analysis of large analog circuits. DAC 2004: 860-863
1	EE	Sheldon X.-D. Tan, Zhenyu Qi, Hang Li: Hierarchical Modeling and Simulation of Large Analog Circuits. DATE 2004: 740-741

Coauthor Index

1	Travis N. Blalock	[18]
2	Adam C. Cabe	[18]
3	Yici Cai	[5] [9] [13]
4	Gary S. Ditlow	[16]
5	Jeffrey Fan	[13]
6	Weikun Guo	[2] [3]
7	Lei He	[7] [10] [11] [12]
8	Xianlong Hong	[5] [9] [13]
9	Lingling Jin	[6] [8]
10	Jun Kong	[7]
11	Stephen V. Kosonocky	[15] [16]
12	Hang Li	[1] [5] [6] [7] [8] [9] [13]
13	Pu Liu	[4] [6] [7] [8] [12]
14	Bruce McGaughy	[7]
15	Jan M. Rabaey	[15]
16	Mircea R. Stan	[15] [16] [17] [18]
17	Sheldon X.-D. Tan (Xiang-Dong Tan)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]
18	Stuart N. Wooters	[18]
19	Lifeng Wu	[5] [9] [13]
20	Wei Wu	[6] [8]
21	Jing Xu	[14]
22	Jun Yang	[6] [8]
23	Hao Yu	[10] [11] [12]
24	Matthew M. Ziegler	[15] [16]

Colors in the list of coauthors