2008 |
19 | EE | Rishad A. Shafik,
Paul M. Rosinger,
Bashir M. Al-Hashimi:
MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC.
DDECS 2008: 98-103 |
18 | EE | S. Saqib Khursheed,
Urban Ingelsson,
Paul M. Rosinger,
Bashir M. Al-Hashimi,
Peter Harrod:
Bridging Fault Test Method With Adaptive Power Management Awareness.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1117-1127 (2008) |
17 | EE | Zhiyuan He,
Zebo Peng,
Petru Eles,
Paul M. Rosinger,
Bashir M. Al-Hashimi:
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.
J. Electronic Testing 24(1-3): 247-257 (2008) |
2007 |
16 | EE | Alireza Ejlali,
Bashir M. Al-Hashimi,
Paul M. Rosinger,
Seyed Ghassem Miremadi:
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks.
DATE 2007: 1647-1652 |
15 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Rapid Generation of Thermal-Safe Test Schedules
CoRR abs/0710.4797: (2007) |
2006 |
14 | EE | Luigi Dilillo,
Paul M. Rosinger,
Bashir M. Al-Hashimi,
Patrick Girard:
Minimizing test power in SRAM through reduction of pre-charge activity.
DATE 2006: 1159-1164 |
13 | EE | Zhiyuan He,
Zebo Peng,
Petru Eles,
Paul M. Rosinger,
Bashir M. Al-Hashimi:
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.
DFT 2006: 477-485 |
12 | EE | Alireza Ejlali,
Bashir M. Al-Hashimi,
Marcus T. Schmitz,
Paul M. Rosinger,
Seyed Ghassem Miremadi:
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.
IEEE Trans. VLSI Syst. 14(4): 323-335 (2006) |
11 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2502-2512 (2006) |
10 | EE | Luigi Dilillo,
Paul M. Rosinger,
Bashir M. Al-Hashimi,
Patrick Girard:
Reducing Power Dissipation in SRAM during Test.
J. Low Power Electronics 2(2): 271-280 (2006) |
2005 |
9 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Rapid Generation of Thermal-Safe Test Schedules.
DATE 2005: 840-845 |
8 | EE | Enkelejda Tafaj,
Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling.
DFT 2005: 544-551 |
7 | EE | Alireza Ejlali,
Marcus T. Schmitz,
Bashir M. Al-Hashimi,
Seyed Ghassem Miremadi,
Paul M. Rosinger:
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy.
ISLPED 2005: 281-286 |
2004 |
6 | EE | Matheos Lampropoulos,
Bashir M. Al-Hashimi,
Paul M. Rosinger:
Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique.
DATE 2004: 1372-1373 |
5 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1142-1153 (2004) |
2002 |
4 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Scan Architecture for Shift and Capture Cycle Power Reduction.
DFT 2002: 129-137 |
3 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding.
ICCD 2002: 474-479 |
2 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Power profile manipulation: a new approach for reducing test application time under power constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1217-1225 (2002) |
2001 |
1 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Power constrained test scheduling using power profile manipulation.
ISCAS (5) 2001: 251-254 |