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Janet Meiling Wang Roveda
List of publications from the DBLP Bibliography Server - FAQ
2009 | ||
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53 | EE | Jin Sun, Avinash Kodi, Ahmed Louri, Janet Meiling Wang: NBTI aware workload balancing in multi-core systems. ISQED 2009: 833-838 |
2008 | ||
52 | EE | Jin Sun, Yue Huang, Jun Li, Janet Meiling Wang: Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty. ASP-DAC 2008: 531-536 |
51 | EE | Sridhar Varadan, Janet Meiling Wang, Jiang Hu: Handling partial correlations in yield prediction. ASP-DAC 2008: 543-548 |
50 | EE | Dinesh Ganesan, Alexander V. Mitev, Janet Meiling Wang, Yu Cao: Finite-Point Gate Model for Fast Timing and Power Analysis. ISQED 2008: 657-662 |
49 | EE | Kishore Kumar Muchherla, Pinhong Chen, Dongsheng Ma, Janet Meiling Wang: A noniterative equivalent waveform model for timing analysis in presence of crosstalk. ACM Trans. Design Autom. Electr. Syst. 13(2): (2008) |
48 | EE | Jin Sun, Jun Li, Dongsheng Ma, Janet Meiling Wang: Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty. IEEE Trans. on CAD of Integrated Circuits and Systems 27(10): 1852-1865 (2008) |
47 | EE | Uday Padmanabhan, Janet Meiling Wang, Jiang Hu: Robust Clock Tree Routing in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1385-1397 (2008) |
2007 | ||
46 | EE | Alexander V. Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang: Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) Method. ASP-DAC 2007: 468-473 |
45 | EE | Vineet Agarwal, Jin Sun, Alexander V. Mitev, Janet Meiling Wang: Delay Uncertainty Reduction by Interconnect and Gate Splitting. ASP-DAC 2007: 690-695 |
44 | EE | Alexander V. Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang: Principle Hessian direction based parameter reduction with process variation. ICCAD 2007: 632-637 |
43 | EE | Alexander V. Mitev, Dinesh Ganesan, Dheepan Shanmugasundaram, Yu Cao, Janet Meiling Wang: A robust finite-point based gate model considering process variations. ICCAD 2007: 692-697 |
42 | EE | Alexander V. Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang: Principle hessian direction based parameter reduction for interconnect networks with process variation. SLIP 2007: 41-46 |
41 | EE | Bharat Sukhwani, Uday Padmanabhan, Janet Meiling Wang: Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design CoRR abs/0710.4633: (2007) |
40 | EE | Y. Satish Kumar, Jun Li, Claudio Talarico, Janet Meiling Wang: A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching CoRR abs/0710.4634: (2007) |
39 | EE | Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang: Stochastic Power Grid Analysis Considering Process Variations CoRR abs/0710.4649: (2007) |
2006 | ||
38 | EE | Vineet Agarwal, Janet Meiling Wang: Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA). ASP-DAC 2006: 718-723 |
37 | EE | Navneeth Kankani, Vineet Agarwal, Janet Meiling Wang: A probabilistic analysis of pipelined global interconnect under process variations. ASP-DAC 2006: 724-729 |
36 | EE | Dongsheng Ma, Janet Meiling Wang, Pablo Vazquas: Adaptive on-chip power supply with robust one-cycle control technique. ISLPED 2006: 394-399 |
35 | EE | Uday Padmanabhan, Janet Meiling Wang, Jiang Hu: Statistical clock tree routing for robustness to process variations. ISPD 2006: 149-156 |
34 | EE | Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta: Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2001-2011 (2006) |
33 | EE | Janet Meiling Wang, Jun Li, Satish K. Yanamanamanda, Lakshmi Kalpana Vakati, Kishore Kumar Muchherla: Modeling the Driver Load in the Presence of Process Variations. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2264-2275 (2006) |
2005 | ||
32 | EE | Vineet Agarwal, Navneeth Kankani, Ravishankar Rao, Sarvesh Bhardwaj, Janet Meiling Wang: An efficient combinationality check technique for the synthesis of cyclic combinational circuits. ASP-DAC 2005: 212-215 |
31 | EE | Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda: A perturbation-aware noise convergence methodology for high frequency microprocessors. ASP-DAC 2005: 717-722 |
30 | EE | Bharat B. Sukhwani, Uday Padmanabhan, Janet Meiling Wang: Nano-Sim: A Step Wise Equivalent Conductance based Statistical Simulator for Nanotechnology Circuit Design. DATE 2005: 758-763 |
29 | EE | Y. Satish Kumar, Jun Li, Claudio Talarico, Janet Meiling Wang: A Probabilistic Collocation Method Based Statistical Gate Delay Model Considering Process Variations and Multiple Input Switching. DATE 2005: 770-775 |
28 | EE | Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang: Stochastic Power Grid Analysis Considering Process Variations. DATE 2005: 964-969 |
27 | Rong Jiang, Wenyin Fu, Janet Meiling Wang, Vince Lin, Charlie Chung-Ping Chen: Efficient statistical capacitance variability modeling with orthogonal principle factor analysis. ICCAD 2005: 683-690 | |
26 | Janet Meiling Wang, Bharat Srinivas, Dongsheng Ma, Charlie Chung-Ping Chen, Jun Li: System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). ICCAD 2005: 728-735 | |
25 | EE | Satish K. Yanamanamanda, Jun Li, Janet Meiling Wang: Uncertainty modeling of gate delay considering multiple input switching. ISCAS (3) 2005: 2457-2460 |
24 | EE | Kishore Kumar Muchherla, Pinhong Chen, Janet Meiling Wang: A non-iterative equivalent waveform model for timing analysis in presence of crosstalk. ISCAS (3) 2005: 2465-2468 |
23 | EE | Bharat B. Sukhwani, Janet Meiling Wang: A stepwise constant conductance approach for simulating resonant tunneling diodes. ISCAS (3) 2005: 2518-2521 |
22 | EE | Dongsheng Ma, Janet Meiling Wang, Mohankumar N. Somasundaram, Zongqi Hu: Design and optimization on dynamic power system for self-powered integrated wireless sensing nodes. ISLPED 2005: 303-306 |
21 | EE | Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Meiling Wang, Charlie Chung-Ping Chen: HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 797-806 (2005) |
20 | EE | Lakshmi Kalpana Vakati, Kishore Kumar Muchherla, Janet Meiling Wang: A New Three-Piece Driver Model with RLC Interconnect Load. IEICE Transactions 88-A(8): 2206-2215 (2005) |
2004 | ||
19 | EE | Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang: Realizable parasitic reduction for distributed interconnects using matrix pencil technique. ASP-DAC 2004: 780-785 |
18 | EE | Janet Meiling Wang, Omar Hafiz, Pinhong Chen: A non-iterative model for switching window computation with crosstalk noise. ASP-DAC 2004: 846-851 |
17 | EE | Janet Meiling Wang, Omar Hafiz, Jun Li: A linear fractional transform (LFT) based model for interconnect parametric uncertainty. DAC 2004: 375-380 |
16 | EE | Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang: A methodology to improve timing yield in the presence of process variations. DAC 2004: 448-453 |
15 | EE | Janet Meiling Wang, Praveen Ghanta, Sarma B. K. Vrudhula: Stochastic analysis of interconnect performance in the presence of process variations. ICCAD 2004: 880-886 |
14 | Omar Hafiz, Pinhong Chen, Janet Meiling Wang: A new non-iterative model for switching window computation with crosstalk noise. ISCAS (2) 2004: 497-500 | |
13 | Janet Meiling Wang, Omar Hafiz: Matrix pencil based realizable reduction for distributed interconnects. ISCAS (5) 2004: 177-180 | |
12 | Lakshmi Kalpana Vakati, Janet Meiling Wang: A new multi-ramp driver model with RLC interconnect load. ISCAS (5) 2004: 269-272 | |
11 | EE | Lakshmi Kalpana Vakati, Janet Meiling Wang: A new multi-ramp driver model with RLC interconnect load. ISPD 2004: 170-175 |
10 | EE | Janet Meiling Wang, Kishore Kumar Muchherla, Jai Ganesh Kumar: A Clustering Based Area I/O Planning for Flip-Chip Technology. ISQED 2004: 196-201 |
9 | EE | Janet Meiling Wang, Omar Hafiz: Predicting Interconnect Uncertainty with a New Robust Model Order Reduction Method. ISQED 2004: 363-368 |
2003 | ||
8 | EE | Janet Meiling Wang, Pinhong Chen, Omar Hafiz: A New Continuous Switching Window Computation with Crosstalk Noise. SBCCI 2003: 261-266 |
7 | Janet Meiling Wang, Pinhong Chen, Omar Hafiz: Switching Windows Computation in Presence of Crosstalk Noise. VLSI 2003: 114-118 | |
2000 | ||
6 | EE | Janet Meiling Wang, Tuyen V. Nguyen: Extended Krylov subspace method for reduced order analysis of linear circuits with multiple sources. DAC 2000: 247-252 |
5 | EE | Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh: Passive model order reduction algorithm based on Chebyshev expansion of impulse response of interconnect networks. DAC 2000: 520-525 |
1999 | ||
4 | EE | Janet Meiling Wang, Qingjian Yu, Ernest S. Kuh: Coupled Noise Estimation for Distributed RC Interconnect Model. DATE 1999: 664-668 |
3 | EE | Janet Meiling Wang, Ernest S. Kuh, Qingjian Yu: The Chebyshev expansion based passive model for distributed interconnect networks. ICCAD 1999: 370-375 |
1998 | ||
2 | EE | Qingjian Yu, Janet Meiling Wang, Ernest S. Kuh: Multipoint moment matching model for multiport distributed interconnect networks. ICCAD 1998: 85-91 |
1996 | ||
1 | EE | Jun-Fa Mao, Janet Meiling Wang, Ernest S. Kuh: Simulation and sensitivity analysis of transmission line circuits by the characteristics method. ICCAD 1996: 556-562 |