Milos Hrkic

2006
13	EE	Hosung (Leo) Kim, John Lillis, Milos Hrkic: Techniques for improved placement-coupled logic replication. ACM Great Lakes Symposium on VLSI 2006: 211-216
12	EE	Milos Hrkic, John Lillis, Giancarlo Beraudo: An Approach to Placement-Coupled Logic Replication. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2539-2551 (2006)
2004
11	EE	Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay: Fast and flexible buffer trees that navigate the physical layout environment. DAC 2004: 24-29
10	EE	Milos Hrkic, John Lillis, Giancarlo Beraudo: An approach to placement-coupled logic replication. DAC 2004: 711-716
9	EE	Charles J. Alpert, Milos Hrkic, Stephen T. Quay: A fast algorithm for identifying good buffer insertion candidate locations. ISPD 2004: 47-52
8	EE	Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004)
7	EE	Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze: Porosity-aware buffered Steiner tree construction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 517-526 (2004)
2003
6	EE	Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay: Porosity aware buffered steiner tree construction. ISPD 2003: 158-165
5	EE	Milos Hrkic, John Lillis: Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 481-491 (2003)
2002
4	EE	Milos Hrkic, John Lillis: S-Tree: a technique for buffered routing tree synthesis. DAC 2002: 578-583
3	EE	Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay: Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. ISPD 2002: 104-109
2	EE	Milos Hrkic, John Lillis: Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost and blockages. ISPD 2002: 98-103
2001
1	EE	Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia: Buffered Steiner trees for difficult instances. ISPD 2001: 4-9

Coauthor Index

1	Charles J. Alpert	[1] [3] [6] [7] [8] [9] [11]
2	Giancarlo Beraudo	[10] [12]
3	Chris C. N. Chu (Chris Chong-Nuen Chu)	[3] [8]
4	Gopal Gandham	[3] [6] [7] [8]
5	Jiang Hu	[1] [3] [6] [7] [8] [11]
6	Andrew B. Kahng	[1]
7	Chandramouli V. Kashyap	[3] [8]
8	Hosung (Leo) Kim	[13]
9	John Lillis	[1] [2] [4] [5] [10] [12] [13]
10	Bao Liu	[1]
11	Stephen T. Quay	[1] [3] [6] [7] [8] [9] [11]
12	Sachin S. Sapatnekar	[1]
13	A. J. Sullivan	[1]
14	Cliff C. N. Sze (Chin Ngai Sze, Cliff N. Sze)	[7]
15	Paul G. Villarrubia (Paul Villarrubia)	[1]