Unai Bidarte

2009
12	EE	Jesús Lázaro, Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga: AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. ARC 2009: 312-317
2008
11	EE	Armando Astarloa, Unai Bidarte, Jaime Jimenez, Jesús Lázaro, Iñigo Martínez de Alegría: Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes. ATC 2008: 603-614
2007
10	EE	Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, Jaime Jimenez: Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. Journal of Systems Architecture 53(9): 629-643 (2007)
9	EE	Jesús Lázaro, Jagoba Arias, Armando Astarloa, Unai Bidarte, Aitzol Zuloaga: Hardware architecture for a general regression neural network coprocessor. Neurocomputing 71(1-3): 78-87 (2007)
2006
8	EE	Jaime Jimenez, José Luis Martín, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias: Comparison of two designs for the multifunction vehicle bus. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 797-805 (2006)
2005
7	EE	José L. Martín-Sánchez, Aitzol Zuloaga, Carlos Cuadrado, Jesús Lázaro, Unai Bidarte: Hardware implementation of optical flow constraint equation using FPGAs. Computer Vision and Image Understanding 98(3): 462-490 (2005)
6	EE	Armando Astarloa, Unai Bidarte, Jesús Lázaro, Aitzol Zuloaga, Jagoba Arias: Multiprocessor SoPC-Core for FAT volume computation. Microprocessors and Microsystems 29(10): 421-434 (2005)
2004
5	EE	Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga: A Self-Reconfiguration Framework for Multiprocessor CSoPCs. FPL 2004: 1124-1126
4	EE	Unai Bidarte, Armando Astarloa, José Luis Martín, Jon Andreu: Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design. FPL 2004: 965-969
3	EE	Jesús Lázaro, Armando Astarloa, Jagoba Arias, Unai Bidarte, Carlos Cuadrado: High Throughput Serpent Encryption Implementation. FPL 2004: 996-1000
2		Armando Astarloa, Jesús Lázaro, Jagoba Arias, Unai Bidarte, Aitzol Zuloaga: Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. MSV/AMCS 2004: 17-22
2003
1	EE	Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría: Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. FPL 2003: 497-506

Coauthor Index

1	Iñigo Martínez de Alegría	[1] [11]
2	Jon Andreu	[4]
3	Jagoba Arias	[2] [3] [6] [8] [9]
4	Armando Astarloa	[1] [2] [3] [4] [5] [6] [9] [10] [11] [12]
5	Carlos Cuadrado	[3] [7]
6	Jaime Jimenez	[1] [8] [10] [11] [12]
7	Jesús Lázaro	[2] [3] [5] [6] [7] [9] [10] [11] [12]
8	José Luis Martín	[4] [5] [8] [10]
9	José L. Martín-Sánchez	[7]
10	Aitzol Zuloaga	[1] [2] [5] [6] [7] [8] [9] [10] [12]