| 2009 |
|---|
| 88 | EE | S. Saqib Khursheed,
Bashir M. Al-Hashimi,
Sudhakar M. Reddy,
Peter Harrod:
Diagnosis of Multiple-Voltage Design With Bridge Defect.
IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 406-416 (2009) |
| 2008 |
|---|
| 87 | EE | Aiman H. El-Maleh,
Bashir M. Al-Hashimi,
Aissa Melouki:
Transistor-level based defect tolerance for reliable nanoelectronics.
AICCSA 2008: 53-60 |
| 86 | EE | Simon Ogg,
Bashir M. Al-Hashimi,
Alexandre Yakovlev:
Asynchronous transient resilient links for NoC.
CODES+ISSS 2008: 209-214 |
| 85 | EE | Simon Ogg,
Enrico Valli,
Bashir M. Al-Hashimi,
Alexandre Yakovlev,
Crescenzo D'Alessandro,
Luca Benini:
Serialized Asynchronous Links for NoC.
DATE 2008: 1003-1008 |
| 84 | EE | Tom J. Kazmierski,
Dafeng Zhou,
Bashir M. Al-Hashimi:
Efficient circuit-level modelling of ballistic CNT using piecewise non-linear approximation of mobile charge density.
DATE 2008: 146-151 |
| 83 | EE | Leran Wang,
Tom J. Kazmierski,
Bashir M. Al-Hashimi,
Stephen P. Beeby,
Russel N. Torah:
Integrated approach to energy harvester mixed technology modelling and performance optimisation.
DATE 2008: 704-709 |
| 82 | EE | Rishad A. Shafik,
Paul M. Rosinger,
Bashir M. Al-Hashimi:
MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC.
DDECS 2008: 98-103 |
| 81 | EE | Dafeng Zhou,
Tom J. Kazmierski,
Bashir M. Al-Hashimi:
VHDL-AMS Implementation of a Numerical Ballistic CNT Model for Logic Circuit Simulation.
FDL 2008: 94-98 |
| 80 | EE | Alireza Ejlali,
Bashir M. Al-Hashimi:
SEU-Hardened Energy Recovery Pipelined Interconnects for On-Chip Networks.
NOCS 2008: 67-76 |
| 79 | EE | Biswajit Mishra,
Bashir M. Al-Hashimi:
Subthreshold FIR Filter Architecture for Ultra Low Power Applications.
PATMOS 2008: 1-10 |
| 78 | EE | S. Saqib Khursheed,
Urban Ingelsson,
Paul M. Rosinger,
Bashir M. Al-Hashimi,
Peter Harrod:
Bridging Fault Test Method With Adaptive Power Management Awareness.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1117-1127 (2008) |
| 77 | EE | Zhiyuan He,
Zebo Peng,
Petru Eles,
Paul M. Rosinger,
Bashir M. Al-Hashimi:
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.
J. Electronic Testing 24(1-3): 247-257 (2008) |
| 2007 |
|---|
| 76 | EE | M. A. Ochoa-Montiel,
Bashir M. Al-Hashimi,
P. Kollig:
Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection.
ASP-DAC 2007: 517-522 |
| 75 | EE | Alireza Ejlali,
Bashir M. Al-Hashimi,
Paul M. Rosinger,
Seyed Ghassem Miremadi:
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks.
DATE 2007: 1647-1652 |
| 74 | | Luigi Dilillo,
Bashir M. Al-Hashimi:
March CRF: an Efficient Test for Complex Read Faults in SRAM Memories.
DDECS 2007: 173-178 |
| 73 | EE | Haider Ali,
Bashir M. Al-Hashimi:
Architecture Level Power-Performance Tradeoffs for Pipelined Designs.
ISCAS 2007: 1791-1794 |
| 72 | EE | Yuan Cai,
Sudhakar M. Reddy,
Bashir M. Al-Hashimi:
Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint.
ISQED 2007: 368-373 |
| 71 | EE | Simon Ogg,
Enrico Valli,
Crescenzo D'Alessandro,
Alexandre Yakovlev,
Bashir M. Al-Hashimi,
Luca Benini:
Reducing Interconnect Cost in NoC through Serialized Asynchronous Links.
NOCS 2007: 219 |
| 70 | EE | Yuan Cai,
Marcus T. Schmitz,
Bashir M. Al-Hashimi,
Sudhakar M. Reddy:
Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints.
ACM Trans. Design Autom. Electr. Syst. 12(1): (2007) |
| 69 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Rapid Generation of Thermal-Safe Test Schedules
CoRR abs/0710.4797: (2007) |
| 68 | EE | Alexandru Andrei,
Petru Eles,
Zebo Peng,
Marcus T. Schmitz,
Bashir M. Al-Hashimi:
Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection.
IEEE Trans. VLSI Syst. 15(3): 262-275 (2007) |
| 2006 |
|---|
| 67 | EE | Dong Wu,
Bashir M. Al-Hashimi,
Marcus T. Schmitz:
Improving routing efficiency for network-on-chip through contention-aware input selection.
ASP-DAC 2006: 36-41 |
| 66 | EE | Yuan Cai,
Marcus T. Schmitz,
Alireza Ejlali,
Bashir M. Al-Hashimi,
Sudhakar M. Reddy:
Cache size selection for performance, energy and reliability of time-constrained systems.
ASP-DAC 2006: 923-928 |
| 65 | EE | Luigi Dilillo,
Paul M. Rosinger,
Bashir M. Al-Hashimi,
Patrick Girard:
Minimizing test power in SRAM through reduction of pre-charge activity.
DATE 2006: 1159-1164 |
| 64 | EE | Zhiyuan He,
Zebo Peng,
Petru Eles,
Paul M. Rosinger,
Bashir M. Al-Hashimi:
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.
DFT 2006: 477-485 |
| 63 | EE | Matthew Collins,
Bashir M. Al-Hashimi:
On-Chip Time Measurement Architecture with Femtosecond Timing Resolution.
European Test Symposium 2006: 103-110 |
| 62 | EE | Noohul Basheer Zain Ali,
Mark Zwolinski,
Bashir M. Al-Hashimi,
Peter Harrod:
Dynamic Voltage Scaling Aware Delay Fault Testing.
European Test Symposium 2006: 15-20 |
| 61 | EE | Zhuo Zhang,
Sudhakar M. Reddy,
Irith Pomeranz,
Janusz Rajski,
Bashir M. Al-Hashimi:
Enhancing Delay Fault Coverage through Low Power Segmented Scan.
European Test Symposium 2006: 21-28 |
| 60 | EE | Simon Ogg,
Bashir M. Al-Hashimi:
Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal.
VLSI Design 2006: 525-529 |
| 59 | EE | Mauricio Varea,
Bashir M. Al-Hashimi,
Luis Alejandro Cortés,
Petru Eles,
Zebo Peng:
Dual Flow Nets: Modeling the control/data-flow relation in embedded systems.
ACM Trans. Embedded Comput. Syst. 5(1): 54-81 (2006) |
| 58 | EE | Mitra Subhasish,
Ondrej Novák,
Hana Kubatova,
Bashir M. Al-Hashimi,
Erik Jan Marinissen,
C. P. Ravikumar:
Conference Reports.
IEEE Design & Test of Computers 23(4): 262-265 (2006) |
| 57 | EE | Alireza Ejlali,
Bashir M. Al-Hashimi,
Marcus T. Schmitz,
Paul M. Rosinger,
Seyed Ghassem Miremadi:
Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems.
IEEE Trans. VLSI Syst. 14(4): 323-335 (2006) |
| 56 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Thermal-Safe Test Scheduling for Core-Based System-on-Chip Integrated Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2502-2512 (2006) |
| 55 | EE | Bashir M. Al-Hashimi,
Dimitris Gizopoulos,
Manoj Sachdev,
Adit D. Singh:
New JETTA Editors, 2006.
J. Electronic Testing 22(1): 9-10 (2006) |
| 54 | EE | Luigi Dilillo,
Paul M. Rosinger,
Bashir M. Al-Hashimi,
Patrick Girard:
Reducing Power Dissipation in SRAM during Test.
J. Low Power Electronics 2(2): 271-280 (2006) |
| 2005 |
|---|
| 53 | EE | Alexandru Andrei,
Marcus T. Schmitz,
Petru Eles,
Zebo Peng,
Bashir M. Al-Hashimi:
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints.
DATE 2005: 514-519 |
| 52 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Rapid Generation of Thermal-Safe Test Schedules.
DATE 2005: 840-845 |
| 51 | EE | Enkelejda Tafaj,
Paul M. Rosinger,
Bashir M. Al-Hashimi,
Krishnendu Chakrabarty:
Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling.
DFT 2005: 544-551 |
| 50 | EE | Dong Wu,
Bashir M. Al-Hashimi,
Marcus T. Schmitz,
Petru Eles:
Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction.
DSD 2005: 34-41 |
| 49 | EE | Yuan Cai,
Sudhakar M. Reddy,
Irith Pomeranz,
Bashir M. Al-Hashimi:
Battery-aware dynamic voltage scaling in multiprocessor embedded system.
ISCAS (1) 2005: 616-619 |
| 48 | EE | Peter Wilson,
Reuben Wilcock,
Bashir M. Al-Hashimi:
A novel switched-current phase locked loop.
ISCAS (3) 2005: 2815-2818 |
| 47 | EE | M. A. Ochoa-Montiel,
Bashir M. Al-Hashimi,
P. Kollig:
Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis.
ISCAS (4) 2005: 4163-4166 |
| 46 | EE | Mehdi Jafaripanah,
Bashir M. Al-Hashimi,
Neil M. White:
Adaptive sensor response correction using analog filter compatible with digital technology [load cell sensor applications].
ISCAS (6) 2005: 5389-5392 |
| 45 | EE | Alireza Ejlali,
Marcus T. Schmitz,
Bashir M. Al-Hashimi,
Seyed Ghassem Miremadi,
Paul M. Rosinger:
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy.
ISLPED 2005: 281-286 |
| 44 | EE | Paul Theo Gonciari,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Synchronization overhead in SOC compressed test.
IEEE Trans. VLSI Syst. 13(1): 140-152 (2005) |
| 43 | EE | Marcus T. Schmitz,
Bashir M. Al-Hashimi,
Petru Eles:
Cosynthesis of energy-efficient multimode embedded systems with consideration of mode-execution probabilities.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(2): 153-169 (2005) |
| 2004 |
|---|
| 42 | EE | Matheos Lampropoulos,
Bashir M. Al-Hashimi,
Paul M. Rosinger:
Minimization of Crosstalk Noise, Delay and Power Using a Modified Bus Invert Technique.
DATE 2004: 1372-1373 |
| 41 | EE | Alexandru Andrei,
Marcus T. Schmitz,
Petru Eles,
Zebo Peng,
Bashir M. Al-Hashimi:
Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems.
DATE 2004: 518-525 |
| 40 | EE | Alexandru Andrei,
Marcus T. Schmitz,
Petru Eles,
Zebo Peng,
Bashir M. Al-Hashimi:
Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems.
ICCAD 2004: 362-369 |
| 39 | | Reuben Wilcock,
Bashir M. Al-Hashimi:
Power-conscious design methodology for class-A switched-current wave filters.
ISCAS (1) 2004: 225-228 |
| 38 | EE | Yan Xie,
Bashir M. Al-Hashimi:
Analogue adaptive filters using wave synthesis technique.
ISCAS (1) 2004: 849-852 |
| 37 | EE | Geoff Merrett,
Bashir M. Al-Hashimi:
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates.
PATMOS 2004: 198-207 |
| 36 | EE | Marcus T. Schmitz,
Bashir M. Al-Hashimi,
Petru Eles:
Iterative schedule optimization for voltage scalable distributed embedded systems.
ACM Trans. Embedded Comput. Syst. 3(1): 182-217 (2004) |
| 35 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Scan architecture with mutually exclusive scan segment activation for shift- and capture-power reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(7): 1142-1153 (2004) |
| 34 | EE | Nicola Nicolici,
Bashir M. Al-Hashimi:
Testability Trade-Offs for BIST Data Paths.
J. Electronic Testing 20(2): 169-179 (2004) |
| 2003 |
|---|
| 33 | EE | Dong Wu,
Bashir M. Al-Hashimi,
Petru Eles:
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems.
DATE 2003: 10090-10095 |
| 32 | EE | Petros Oikonomakos,
Mark Zwolinski,
Bashir M. Al-Hashimi:
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric.
DATE 2003: 10596-10601 |
| 31 | EE | Paul Theo Gonciari,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Test Data Compression: The System Integrator's Perspective.
DATE 2003: 10726-10731 |
| 30 | EE | Marcus T. Schmitz,
Bashir M. Al-Hashimi,
Petru Eles:
A Co-Design Methodology for Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities.
DATE 2003: 10960-10965 |
| 29 | EE | Chun-Ming Chang,
Bashir M. Al-Hashimi:
Analytical synthesis of voltage mode OTA-C all-pass filters for high frequency operation.
ISCAS (1) 2003: 461-464 |
| 28 | EE | Mehdi Jafaripanah,
Bashir M. Al-Hashimi,
Neil M. White:
Load cell response correction using analog adaptive techniques.
ISCAS (4) 2003: 752-755 |
| 27 | EE | Nicola Nicolici,
Bashir M. Al-Hashimi:
Power-Conscious Test Synthesis and Scheduling.
IEEE Design & Test of Computers 20(4): 48-55 (2003) |
| 26 | EE | Paul Theo Gonciari,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Addressing useless test data in core-based system-on-a-chip test.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1568-1580 (2003) |
| 25 | EE | Paul Theo Gonciari,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Variable-length input Huffman coding for system-on-a-chip test.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 783-796 (2003) |
| 2002 |
|---|
| 24 | EE | Mauricio Varea,
Bashir M. Al-Hashimi,
Luis Alejandro Cortés,
Petru Eles,
Zebo Peng:
Symbolic model checking of Dual Transition Petri Nets.
CODES 2002: 43-48 |
| 23 | EE | Marcus T. Schmitz,
Bashir M. Al-Hashimi,
Petru Eles:
Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems.
DATE 2002: 514-521 |
| 22 | EE | Paul Theo Gonciari,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression.
DATE 2002: 604-611 |
| 21 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Scan Architecture for Shift and Capture Cycle Power Reduction.
DFT 2002: 129-137 |
| 20 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding.
ICCD 2002: 474-479 |
| 19 | EE | Reuben Wilcock,
Bashir M. Al-Hashimi:
Application of group delay equalisation in testing fully-balanced OTA-C filters.
ISCAS (4) 2002: 643-646 |
| 18 | EE | Paul Theo Gonciari,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Integrated Test Data Decompression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing.
ITC 2002: 64-73 |
| 17 | EE | Paul Theo Gonciari,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Useless Memory Allocation in System-on-a-Chip Test: Problems and Solutions.
VTS 2002: 423-432 |
| 16 | EE | Nicola Nicolici,
Bashir M. Al-Hashimi:
Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits.
IEEE Trans. Computers 51(6): 721-734 (2002) |
| 15 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Power profile manipulation: a new approach for reducing test application time under power constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1217-1225 (2002) |
| 2001 |
|---|
| 14 | EE | Mauricio Varea,
Bashir M. Al-Hashimi:
Dual transitions petri net based modelling technique for embedded systems specification.
DATE 2001: 566-571 |
| 13 | EE | Nicola Nicolici,
Bashir M. Al-Hashimi:
Testability trade-offs for BIST RTL data paths: the case for three dimensional design space.
DATE 2001: 802 |
| 12 | EE | Paul M. Rosinger,
Bashir M. Al-Hashimi,
Nicola Nicolici:
Power constrained test scheduling using power profile manipulation.
ISCAS (5) 2001: 251-254 |
| 11 | | Marcus T. Schmitz,
Bashir M. Al-Hashimi:
Considering power variations of DVS processing elements for energy minimisation in distributed systems.
ISSS 2001: 250-255 |
| 10 | | Nicola Nicolici,
Bashir M. Al-Hashimi:
Tackling test trade-offs for BIST RTL data paths: BIST area overhead, test application time and power dissipation.
ITC 2001: 72-81 |
| 2000 |
|---|
| 9 | EE | Nicola Nicolici,
Bashir M. Al-Hashimi:
Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits.
DATE 2000: 715-722 |
| 8 | | Nicola Nicolici,
Bashir M. Al-Hashimi:
Power conscious test synthesis and scheduling for BIST RTL data paths.
ITC 2000: 662-671 |
| 7 | EE | Nicola Nicolici,
Bashir M. Al-Hashimi,
Andrew D. Brown,
Alan Christopher Williams:
BIST hardware synthesis for RTL data paths based on testcompatibility classes.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(11): 1375-1385 (2000) |
| 1999 |
|---|
| 6 | EE | Nicola Nicolici,
Bashir M. Al-Hashimi:
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths.
DATE 1999: 289- |
| 5 | EE | P. Kollig,
Bashir M. Al-Hashimi:
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs.
FPGA 1999: 227-234 |
| 4 | EE | J. Living,
Bashir M. Al-Hashimi:
Mixed arithmetic architecture: a solution to the iteration bound for resource efficient FPGA and CPLD recursive digital filters.
ISCAS (1) 1999: 478-481 |
| 3 | EE | F. Dudek,
Bashir M. Al-Hashimi,
M. Moniri:
Compensation of nonideal effects in video-frequency sinc(x)-equalizers using tunable gm-C structure.
ISCAS (2) 1999: 148-151 |
| 2 | EE | J. Living,
Bashir M. Al-Hashimi:
New differential coefficient coding algorithm for recursive FIR filters.
ISCAS (3) 1999: 379-382 |
| 1998 |
|---|
| 1 | | Nicola Nicolici,
Bashir M. Al-Hashimi:
Correction to the Proof of Theorem 2 in ``Parallel Signature Analysis Design with Bounds on Aliasing.
IEEE Trans. Computers 47(12): 1426 (1998) |
