| 2009 |
|---|
| 72 | EE | Uday Doddannagari,
Shiyan Hu,
Weiping Shi:
Fast characterization of parameterized cell library.
ISQED 2009: 500-505 |
| 71 | EE | Ying Zhou,
Rouwaida Kanj,
Kanak Agarwal,
Zhuo Li,
Rajiv V. Joshi,
Sani R. Nassif,
Weiping Shi:
The impact of BEOL lithography effects on the SRAM cell performance and yield.
ISQED 2009: 607-612 |
| 2008 |
|---|
| 70 | EE | Zhanyuan Jiang,
Weiping Shi:
Circuit-wise buffer insertion and gate sizing algorithm with scalability.
DAC 2008: 708-713 |
| 69 | EE | Rouwaida Kanj,
Rajiv V. Joshi,
Zhou Li,
Jente B. Kuang,
Hung C. Ngo,
Ying Zhou,
Weiping Shi,
Sani R. Nassif:
SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.
ISLPED 2008: 87-92 |
| 68 | EE | Yifang Liu,
Jiang Hu,
Weiping Shi:
Multi-scenario buffer insertion in multi-core processor designs.
ISPD 2008: 15-22 |
| 67 | EE | Yang Yi,
Peng Li,
Vivek Sarin,
Weiping Shi:
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(11): 1918-1927 (2008) |
| 66 | EE | Yifang Liu,
Jiang Hu,
Weiping Shi:
Buffering Interconnect for Multicore Processor Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2183-2196 (2008) |
| 2007 |
|---|
| 65 | EE | Ying Zhou,
Zhuo Li,
Yuxin Tian,
Weiping Shi,
Frank Liu:
A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects.
ASP-DAC 2007: 450-455 |
| 64 | EE | Zhanyuan Jiang,
Shiyan Hu,
Weiping Shi:
A New Twisted Differential Line Structure in Global Bus Design.
DAC 2007: 180-183 |
| 63 | EE | Ying Zhou,
Zhuo Li,
Weiping Shi:
Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method.
DAC 2007: 835-840 |
| 62 | EE | Yang Yi,
Peng Li,
Vivek Sarin,
Weiping Shi:
Impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method.
ICCAD 2007: 7-10 |
| 61 | EE | Zhanyuan Jiang,
Shiyan Hu,
Jiang Hu,
Weiping Shi:
An Efficient Algorithm for RLC Buffer Insertion.
ISQED 2007: 171-175 |
| 60 | EE | Zhuo Li,
Charles J. Alpert,
Stephen T. Quay,
Sachin S. Sapatnekar,
Weiping Shi:
Probabilistic Congestion Prediction with Partial Blockages.
ISQED 2007: 841-846 |
| 59 | EE | Zhuo Li,
Weiping Shi:
An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types
CoRR abs/0710.4691: (2007) |
| 58 | EE | Shiyan Hu,
Charles J. Alpert,
Jiang Hu,
Shrirang K. Karandikar,
Zhuo Li,
Weiping Shi,
Chin-Ngai Sze:
Fast Algorithms for Slew-Constrained Minimum Cost Buffering.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2009-2022 (2007) |
| 57 | EE | Zhuo Li,
Ying Zhou,
Weiping Shi:
Wire Sizing for Non-Tree Topology.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 872-880 (2007) |
| 56 | EE | Chin-Ngai Sze,
Charles J. Alpert,
Jiang Hu,
Weiping Shi:
Path-Based Buffer Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1346-1355 (2007) |
| 2006 |
|---|
| 55 | EE | Zhuo Li,
Weiping Shi:
An O(mn) time algorithm for optimal buffer insertion of nets with m sinks.
ASP-DAC 2006: 320-325 |
| 54 | EE | Peng Li,
Weiping Shi:
Model order reduction of linear networks with massive ports via frequency-dependent port packing.
DAC 2006: 267-272 |
| 53 | EE | Mandar Waghmode,
Zhuo Li,
Weiping Shi:
Buffer insertion in large circuits with constructive solution search techniques.
DAC 2006: 296-301 |
| 52 | EE | Shiyan Hu,
Charles J. Alpert,
Jiang Hu,
Shrirang K. Karandikar,
Zhuo Li,
Weiping Shi,
Cliff C. N. Sze:
Fast algorithms for slew constrained minimum cost buffering.
DAC 2006: 308-313 |
| 51 | EE | Zhanyuan Jiang,
Shiyan Hu,
Jiang Hu,
Zhuo Li,
Weiping Shi:
A new RLC buffer insertion algorithm.
ICCAD 2006: 553-557 |
| 50 | EE | Mandar Waghmode,
Kanupriya Gulati,
Sunil P. Khatri,
Weiping Shi:
An Efficient, Scalable Hardware Engine for Boolean SATisfiability.
ICCD 2006 |
| 49 | EE | Shu Yan,
Vivek Sarin,
Weiping Shi:
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2282-2286 (2006) |
| 48 | EE | Zhuo Li,
Weiping Shi:
An O(bn/sup 2/) time algorithm for optimal buffer insertion with b buffer types.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 484-489 (2006) |
| 2005 |
|---|
| 47 | EE | Zhuo Li,
Cliff C. N. Sze,
Charles J. Alpert,
Jiang Hu,
Weiping Shi:
Making fast buffer insertion even faster via approximation techniques.
ASP-DAC 2005: 13-18 |
| 46 | EE | Cliff C. N. Sze,
Charles J. Alpert,
Jiang Hu,
Weiping Shi:
Path based buffer insertion.
DAC 2005: 509-514 |
| 45 | EE | Zhuo Li,
Weiping Shi:
An O(bn2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types.
DATE 2005: 1324-1329 |
| 44 | EE | Jing Wang,
Xiang Lu,
Wangqi Qiu,
Ziding Yue,
Steve Fancler,
Weiping Shi,
D. M. H. Walker:
Static Compaction of Delay Tests Considering Power Supply Noise.
VTS 2005: 235-240 |
| 43 | EE | Xiang Lu,
Zhuo Li,
Wangqi Qiu,
D. M. H. Walker,
Weiping Shi:
Longest-path selection for delay test under process variation.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1924-1929 (2005) |
| 42 | EE | Weiping Shi,
Zhuo Li:
A fast algorithm for optimal buffer insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 879-891 (2005) |
| 41 | EE | Shu Yan,
Vivek Sarin,
Weiping Shi:
Sparse transformations and preconditioners for 3-D capacitance extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1420-1426 (2005) |
| 40 | EE | Weiping Shi,
Chen Su:
The Rectilinear Steiner Arborescence Problem Is NP-Complete.
SIAM J. Comput. 35(3): 729-740 (2005) |
| 2004 |
|---|
| 39 | EE | Weiping Shi,
Zhuo Li,
Charles J. Alpert:
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost.
ASP-DAC 2004: 609-614 |
| 38 | EE | Xiang Lu,
Zhuo Li,
Wangqi Qiu,
D. M. H. Walker,
Weiping Shi:
Longest path selection for delay test under process variation.
ASP-DAC 2004: 98-103 |
| 37 | EE | Shu Yan,
Vivek Sarin,
Weiping Shi:
Sparse transformations and preconditioners for hierarchical 3-D capacitance extraction with multiple dielectrics.
DAC 2004: 788-793 |
| 36 | EE | Fangqing Yu,
Weiping Shi:
A Divide-and-Conquer Algorithm for 3D Capacitance Extraction.
ISQED 2004: 253-258 |
| 35 | EE | Xiang Lu,
Zhuo Li,
Wangqi Qiu,
D. M. H. Walker,
Weiping Shi:
PARADE: PARAmetric Delay Evaluation under Process Variation.
ISQED 2004: 276-280 |
| 34 | EE | Wangqi Qiu,
Jing Wang,
D. M. H. Walker,
Divya Reddy,
Zhuo Li,
Weiping Shi,
Hari Balachandran:
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits.
ITC 2004: 223-231 |
| 33 | EE | Xiang Lu,
Zhuo Li,
Wangqi Qiu,
D. M. H. Walker,
Weiping Shi:
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide.
MTV 2004: 97-102 |
| 32 | EE | Wangqi Qiu,
Weiping Shi:
Minimum moment Steiner trees.
SODA 2004: 488-495 |
| 31 | EE | Wangqi Qiu,
Xiang Lu,
Jing Wang,
Zhuo Li,
D. M. H. Walker,
Weiping Shi:
A Statistical Fault Coverage Metric for Realistic Path Delay Faults.
VTS 2004: 37-42 |
| 30 | EE | Weiping Shi,
Fangqing Yu:
A divide-and-conquer algorithm for 3-D capacitance extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1157-1163 (2004) |
| 2003 |
|---|
| 29 | EE | Yuxin Tian,
Michael R. Grimaila,
Weiping Shi,
M. Ray Mercer:
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection Method.
Asian Test Symposium 2003: 354-359 |
| 28 | | Qiushuang Wang,
Beijie Luo,
Guang Zhi,
Dangsheng Huang,
Yong Xu,
Weiping Shi:
The clinical evaluation of the modern technology of computer in echocardiography.
CARS 2003: 1401 |
| 27 | EE | Weiping Shi,
Zhuo Li:
An O(nlogn) time algorithm for optimal buffer insertion.
DAC 2003: 580-585 |
| 26 | EE | Wangqi Qiu,
Xiang Lu,
Zhuo Li,
D. M. H. Walker,
Weiping Shi:
CodSim -- A Combined Delay Fault Simulator.
DFT 2003: 79- |
| 25 | EE | Zhuo Li,
Xiang Lu,
Weiping Shi:
Process variation dimension reduction based on SVD.
ISCAS (4) 2003: 672-675 |
| 24 | EE | Zhuo Li,
Xiang Lu,
Wangqi Qiu,
Weiping Shi,
D. M. H. Walker:
A Circuit Level Fault Model for Resistive Opens and Bridges.
VTS 2003: 379-384 |
| 23 | EE | Zhuo Li,
Xiang Lu,
Wangqi Qiu,
Weiping Shi,
D. M. H. Walker:
A circuit level fault model for resistive bridges.
ACM Trans. Design Autom. Electr. Syst. 8(4): 546-559 (2003) |
| 2002 |
|---|
| 22 | EE | Hemant Mahawar,
Vivek Sarin,
Weiping Shi:
A solenoidal basis method for efficient inductance extraction.
DAC 2002: 751-756 |
| 21 | EE | Hemant Mahawar,
Vivek Sarin,
Weiping Shi:
Fast Inductance Extraction of Large VLSI Circuits.
IPDPS 2002 |
| 20 | EE | Weiping Shi,
Jianguo Liu,
Naveen Kakani,
Tiejun Yu:
A fast hierarchical algorithm for three-dimensional capacitanceextraction.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 330-336 (2002) |
| 2001 |
|---|
| 19 | EE | Weiping Shi,
Douglas B. West:
Structural Diagnosis of Wiring Networks: Finding Connected Components of Unknown Subgraphs.
SIAM J. Discrete Math. 14(4): 510-523 (2001) |
| 2000 |
|---|
| 18 | EE | Weiping Shi,
Chen Su:
The rectilinear Steiner arborescence problem is NP-complete.
SODA 2000: 780-787 |
| 17 | | Farhad Shahrokhi,
Weiping Shi:
On Crossing Sets, Disjoint Sets, and Pagenumber.
J. Algorithms 34(1): 40-53 (2000) |
| 1999 |
|---|
| 16 | | Weiping Shi,
Douglas B. West:
Diagnosis of Wiring Networks: An Optimal Randomized Algorithm for Finding Connected Components of Unknown Graphs.
SIAM J. Comput. 28(5): 1541-1551 (1999) |
| 1998 |
|---|
| 15 | EE | Weiping Shi,
Jianguo Liu,
Naveen Kakani,
Tiejun Yu:
A Fast Hierarchical Algorithm for 3-D Capacitance Extraction.
DAC 1998: 212-217 |
| 1997 |
|---|
| 14 | | Weiping Shi,
Douglas B. West:
Optimal Structural Diagnosis of Wiring Networks.
FTCS 1997: 162-171 |
| 1996 |
|---|
| 13 | | Farhad Shahrokhi,
Weiping Shi:
Efficient Deterministic Algorithms for Embedding Graphs on Books.
COCOON 1996: 162-168 |
| 12 | | Peichen Pan,
Weiping Shi,
C. L. Liu:
Area Minimization for Hierarchical Floorplans.
Algorithmica 15(6): 550-571 (1996) |
| 11 | | Weiping Shi,
Ming-Feng Chang,
W. Kent Fuchs:
Harvest Rate of Reconfigurable Pipelines.
IEEE Trans. Computers 45(10): 1200-1203 (1996) |
| 10 | EE | Weiping Shi:
A fast algorithm for area minimization of slicing floorplans.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(12): 1525-1532 (1996) |
| 1995 |
|---|
| 9 | | Weiping Shi,
Douglas B. West:
Optimal Algorithms for Finding Connected Components of an Unknown Graph.
COCOON 1995: 131-140 |
| 8 | EE | Weiping Shi:
An optimal algorithm for area minimization of slicing floorplans.
ICCAD 1995: 480-484 |
| 7 | EE | Weiping Shi,
W. Kent Fuchs:
Optimal interconnect diagnosis of wiring networks.
IEEE Trans. VLSI Syst. 3(3): 430-436 (1995) |
| 1994 |
|---|
| 6 | | Weiping Shi:
A General Method to Design and Reconfigure Loop-Based Linear Arrays.
DFT 1994: 221-229 |
| 5 | EE | Peichen Pan,
Weiping Shi,
C. L. Liu:
Area minimization for hierarchical floorplans.
ICCAD 1994: 436-440 |
| 1992 |
|---|
| 4 | | Sheila A. Greibach,
Weiping Shi,
Shai Simonson:
Single Tree Grammars.
Theoretical Studies in Computer Science 1992: 73-99 |
| 3 | EE | Weiping Shi,
W. Kent Fuchs:
Probabilistic analysis and algorithms for reconfiguration of memory arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(9): 1153-1160 (1992) |
| 1991 |
|---|
| 2 | | Herbert Edelsbrunner,
Weiping Shi:
An O(n log² h) Time Algorithm for the Three-Dimensional Convex Hull Problem.
SIAM J. Comput. 20(2): 259-269 (1991) |
| 1990 |
|---|
| 1 | | Ming-Feng Chang,
Weiping Shi,
W. Kent Fuchs:
Optimal Diagnosis Procedures for k-out-of-n Structures.
IEEE Trans. Computers 39(4): 559-564 (1990) |
