Jouni Isoaho

2008
39	EE	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho: Area efficient delay-insensitive and differential current sensing on-chip interconnect. SoCC 2008: 143-146
38	EE	Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen: Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation. VLSI Design 2008: 228-234
37	EE	Sampo Tuuna, Li-Rong Zheng, Jouni Isoaho, Hannu Tenhunen: Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid. IEEE Trans. VLSI Syst. 16(6): 766-770 (2008)
36	EE	Muhammad Imran Anwar, Seppo Virtanen, Jouni Isoaho: A software defined approach for common baseband processing. Journal of Systems Architecture - Embedded Systems Design 54(8): 769-786 (2008)
2007
35	EE	Pekka Rantala, Jouni Isoaho, Hannu Tenhunen: Novel Agent-Based Management for Fault-Tolerance in Network-on-Chip. DSD 2007: 551-555
34		Pekka Rantala, Jouni Isoaho, Hannu Tenhunen: Agent-Based Reconfigurability for Fault-Tolerance in Network-on-Chip. ERSA 2007: 207-210
33	EE	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho: Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding. ISCAS 2007: 649-652
2006
32	EE	Tuomo Saarni, Jyri Paakkulainen, Tuomas Mäkilä, Jussi Hakokari, Olli Aaltonen, Jouni Isoaho, Tapio Salakoski: Implementing a Rule-Based Speech Synthesizer on a Mobile Platform. FinTAL 2006: 349-355
31	EE	Tuomo Saarni, Jussi Hakokari, Jouni Isoaho, Olli Aaltonen, Tapio Salakoski: Segmental Duration in Utterance-Initial Environment: Evidence from Finnish Speech Corpora. FinTAL 2006: 576-584
30	EE	Annu Paganus, Vesa-Petteri Mikkonen, Tomi Mäntylä, Sami Nuuttila, Jouni Isoaho, Olli Aaltonen, Tapio Salakoski: The Vowel Game: Continuous Real-Time Visualization for Pronunciation Learning with Vowel Charts. FinTAL 2006: 696-703
29	EE	Teijo Lehtonen, Pekka Rantala, P. Isomaki, Juha Plosila, Jouni Isoaho: An approach for analysing and improving fault tolerance in radio architectures. ISCAS 2006
28	EE	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho: Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic. ISCAS 2006
27	EE	Ethiopia Nigussie, Juha Plosila, Jouni Isoaho: Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling. ISVLSI 2006: 217-224
26	EE	Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen: Analytical model for crosstalk and intersymbol interference in point-to-point buses. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1400-1410 (2006)
2005
25		Seppo Virtanen, Dragos Truscan, Jani Paakkulainen, Jouni Isoaho, Johan Lilius: Highly Automated FPGA Synthesis of Application-Specific Protocol Processors. FPL 2005: 269-274
24	EE	Juha Plosila, Pasi Liljeberg, Jouni Isoaho: Modelling and Refinement of an On-Chip Communication Architecture. ICFEM 2005: 219-234
23	EE	Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen: Case study of interconnect analysis for standing wave oscillator design. ISCAS (1) 2005: 456-459
22	EE	Meigen Shen, Li-Rong Zheng, Esa Tjukanoff, Jouni Isoaho, Hannu Tenhunen: Concurrent Chip Package Design for Global Clock Distribution Network Using Standing Wave Approach. ISQED 2005: 573-578
21	EE	Jari Nurmi, Jan Madsen, Erwin Ofner, Jouni Isoaho, Hannu Tenhunen: The SoC-Mobinet Model in System-on-Chip Education. MSE 2005: 71-72
20	EE	Jani Paakkulainen, Seppo Virtanen, Jouni Isoaho: Tuning a Protocol Processor Architecture Towards DSP Operations. SAMOS 2005: 132-141
2004
19	EE	Pasi Liljeberg, Juha Plosila, Jouni Isoaho: Self-timed communication platform for implementing high-performance systems-on-chip. Integration 38(1): 43-67 (2004)
2003
18		Maria Alaranta, Tuomas Valtonen, Jouni Isoaho: Software for the Changing E-Business. I3E 2003: 103-115
17	EE	Tapani Ahonen, Tero Nurmi, Jari Nurmi, Jouni Isoaho: Block-wise Extraction of Rent's Exponents for an Extensible Processor. ISVLSI 2003: 193-202
16	EE	Sampo Tuuna, Jouni Isoaho: Estimation of Crosstalk Noise for On-Chip Buses. PATMOS 2003: 111-120
15		Johanna Tuominen, Pasi Liljeberg, Jouni Isoaho: Self-Timed Approach for Reducing On-Chip Switching Noise. VLSI-SOC 2003: 19-24
2002
14	EE	Tuomas Valtonen, Jouni Isoaho, Hannu Tenhunen: The Case for Fine-Grained Re-configurable Architectures: An Analysis of Conceived Performance. FPL 2002: 816-825
13	EE	Tuomas Valtonen, Tero Nurmi, Jouni Isoaho, Hannu Tenhunen: Interconnection of autonomous error-tolerant cells. ISCAS (4) 2002: 473-476
12	EE	Pasi Liljeberg, Imed Ben Dhaou, Juha Plosila, Jouni Isoaho, Hannu Tenhunen: Interconnect peak current reduction for wavelet array processor using self-timed signaling. ISCAS (4) 2002: 485-488
2001
11	EE	Pasi Liljeberg, Juha Plosila, Jouni Isoaho: Asynchronous interface for locally clocked modules in ULSI systems. ISCAS (4) 2001: 170-173
10	EE	T. Santti, Jouni Isoaho: Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units. ISCAS (4) 2001: 194-197
9	EE	T. Suutari, Jouni Isoaho, Hannu Tenhunen: High-speed serial communication with error correction using 0.25 um CMOS technology. ISCAS (4) 2001: 618-621
1999
8	EE	Lihong Jia, Yonghong Gao, Jouni Isoaho, Hannu Tenhunen: Design of a super-pipelined Viterbi decoder. ISCAS (1) 1999: 133-136
7	EE	L. Horvath, Imed Ben Dhaou, Hannu Tenhunen, Jouni Isoaho: A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T. ISCAS (4) 1999: 382-385
6	EE	M. Kivioja, Jouni Isoaho, L. Vänskä: Design and Implementation of Viterbi Decoder with FPGAs. VLSI Signal Processing 21(1): 5-14 (1999)
1996
5	EE	Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani: A Rule-Based Approach for Improving Allocation of Filter Structures in HLS. VLSI Design 1996: 133-139
1994
4		Jouni Isoaho, Axel Jantsch, Hannu Tenhunen: DSP Development with Full-Speed Prototyping Based on HW/SW Codesign Techniques. FPL 1994: 318-320
3		Jouni Isoaho, Jari Nurmi: An Overall FIR Filter Optimization Tool for High Granularity Implementation Technologies. ISCAS 1994: 265-268
1993
2	EE	Jouni Isoaho, Jari Pasanen, Olli Vainio, Hannu Tenhunen: DSP system integration and prototyping with FPGAS. VLSI Signal Processing 6(2): 155-172 (1993)
1992
1		Jouni Isoaho, Arto Nummela, Hannu Tenhunen: Technologies and Utilization fo Field Programmable Gate Arrays. FPL 1992: 11-25

Coauthor Index

1	Olli Aaltonen	[30] [31] [32]
2	Tapani Ahonen	[17]
3	Maria Alaranta	[18]
4	Muhammad Imran Anwar	[36]
5	Imed Ben Dhaou	[7] [12]
6	Peeter Ellervee	[5]
7	Yonghong Gao	[8]
8	Jussi Hakokari	[31] [32]
9	Ahmed Hemani	[5]
10	L. Horvath	[7]
11	P. Isomaki	[29]
12	Axel Jantsch	[4] [5]
13	Lihong Jia	[8]
14	M. Kivioja	[6]
15	Teijo Lehtonen	[29]
16	Johan Lilius	[25]
17	Pasi Liljeberg	[11] [12] [15] [19] [24]
18	Jan Madsen	[21]
19	Tuomas Mäkilä	[32]
20	Tomi Mäntylä	[30]
21	Vesa-Petteri Mikkonen	[30]
22	Ethiopia Nigussie	[27] [28] [33] [39]
23	Arto Nummela	[1]
24	Jari Nurmi	[3] [17] [21]
25	Tero Nurmi	[13] [17]
26	Sami Nuuttila	[30]
27	Johnny Öberg	[5]
28	Erwin Ofner	[21]
29	Jani Paakkulainen	[20] [25]
30	Jyri Paakkulainen	[32]
31	Annu Paganus	[30]
32	Jari Pasanen	[2]
33	Juha Plosila	[11] [12] [19] [24] [27] [28] [29] [33] [39]
34	Pekka Rantala	[29] [34] [35]
35	Tuomo Saarni	[31] [32]
36	Tapio Salakoski	[30] [31] [32]
37	T. Santti	[10]
38	Meigen Shen	[22] [23]
39	T. Suutari	[9]
40	Hannu Tenhunen	[1] [2] [4] [7] [8] [9] [12] [13] [14] [21] [22] [23] [26] [34] [35] [37] [38]
41	Esa Tjukanoff	[22] [23]
42	Dragos Truscan	[25]
43	Johanna Tuominen	[15]
44	Sampo Tuuna	[16] [26] [37] [38]
45	Olli Vainio	[2]
46	Tuomas Valtonen	[13] [14] [18]
47	L. Vänskä	[6]
48	Seppo Virtanen	[20] [25] [36]
49	Li-Rong Zheng	[22] [23] [37]

Colors in the list of coauthors