dblp.uni-trier.dewww.uni-trier.de

Animesh Datta

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

2008
11EEAnimesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy: Profit Aware Circuit Design Under Process Variations Considering Speed Binning. IEEE Trans. VLSI Syst. 16(7): 806-815 (2008)
2007
10EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies CoRR abs/0710.4663: (2007)
9EEAnimesh Datta, Ashish Goel, R. T. Cakici, Hamid Mahmoodi, D. Lekshmanan, Kaushik Roy: Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1957-1966 (2007)
2006
8EEAnimesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy: Speed binning aware design methodology to improve profit under parameter variations. ASP-DAC 2006: 712-717
7EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2427-2436 (2006)
2005
6EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy: A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. Asian Test Symposium 2005: 170-175
5EEAnimesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy: Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. DATE 2005: 926-931
4EEAnimesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy: Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. IOLTS 2005: 275-280
3EEAnimesh Datta, Swarup Bhunia, Nilanjan Banerjee, Kaushik Roy: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. ISQED 2005: 358-363
2EESwarup Bhunia, Animesh Datta, Nilanjan Banerjee, Kaushik Roy: GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks. IEEE Trans. Computers 54(6): 752-766 (2005)
1EEAmit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy: A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. VLSI Syst. 13(1): 27-38 (2005)

Coauthor Index

1Amit Agarwal [1]
2Nilanjan Banerjee [2] [3] [5] [10]
3Swarup Bhunia [2] [3] [4] [5] [6] [7] [8] [10] [11]
4R. T. Cakici [9]
5Jung Hwan Choi [8] [11]
6Ashish Goel [9]
7D. Lekshmanan [9]
8Hamid Mahmoodi (Hamid Mahmoodi-Meimand) [1] [9]
9Saibal Mukhopadhyay [4] [5] [6] [7] [8] [10] [11]
10Bipul Chandra Paul (Bipul C. Paul) [1]
11Kaushik Roy [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)