Nadine Azémard

Nadine Azémard-Crestani

2008
31	EE	Bettina Rebaud, Marc Belleville, Christian Bernard, Zequin Wu, Michel Robert, Philippe Maurine, Nadine Azémard: Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier. ISVLSI 2008: 316-321
30	EE	Nadine Azémard, Philippe Maurine, Johan Vounckx: Editorial. Integration 41(1): 1 (2008)
2007
29		Nadine Azémard, Lars J. Svensson: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings Springer 2007
28	EE	B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature and voltage aware timing analysis: application to voltage drops. DATE 2007: 1012-1017
27	EE	V. Migairou, Robin Wilson, S. Engels, Zequin Wu, Nadine Azémard, Philippe Maurine: A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation. PATMOS 2007: 138-147
26	EE	Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol CoRR abs/0710.4760: (2007)
25	EE	B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature- and Voltage-Aware Timing Analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 801-815 (2007)
2006
24		Johan Vounckx, Nadine Azémard, Philippe Maurine: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings Springer 2006
23	EE	Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard: Circuit sizing method under delay constraint. ISCAS 2006
22	EE	B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Timing analysis in presence of supply voltage and temperature variations. ISPD 2006: 10-16
21	EE	V. Migairou, Robin Wilson, S. Engels, Nadine Azémard, Philippe Maurine: Statistical Characterization of Library Timing Performance. PATMOS 2006: 468-476
20	EE	B. Lasbouygues, S. Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Logical effort model extension to propagation delay representation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1677-1684 (2006)
19	EE	S. Engels, Robin Wilson, Nadine Azémard, Philippe Maurine: A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. Integration 39(4): 433-456 (2006)
2005
18	EE	Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol. DATE 2005: 640-645
17	EE	Alexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard: Speed Indicators for Circuit Optimization. PATMOS 2005: 618-628
16	EE	B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine: Temperature Dependency in UDSM Process. PATMOS 2005: 693-703
2004
15		Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Delay bound based CMOS gate sizing technique. ISCAS (5) 2004: 189-192
14	EE	Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Performance Metric Based Optimization Protocol. PATMOS 2004: 100-109
13	EE	B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Temperature Dependence in Low Power CMOS UDSM Process. PATMOS 2004: 110-118
12	EE	A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne: Design Optimization with Automated Cell Generation. PATMOS 2004: 722-731
11	EE	B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Physical Extension of the Logical Effort Model. PATMOS 2004: 838-848
2003
10	EE	Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Metric Definition for Circuit Speed Optimization. PATMOS 2003: 451-460
9	EE	Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: CMOS Gate Sizing under Delay Constraint. PATMOS 2003: 60-69
2002
8	EE	Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne: Gate speed improvement at minimal power dissipation. APCCAS (2) 2002: 325-330
7	EE	Philippe Maurine, Nadine Azémard, Daniel Auvergne: Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS 2002: 247-257
6	EE	Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne: Transition time modeling in deep submicron CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1352-1363 (2002)
2001
5	EE	Nadine Azémard, M. Aline, Daniel Auvergne: Delay bound determination for timing closure satisfaction. ISCAS (5) 2001: 375-378
4		Philippe Maurine, Nadine Azémard, Daniel Auvergne: Gate Sizing for Low Power Design. VLSI-SOC 2001: 301-312
3		Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne: Feasible Delay Bound Definition. VLSI-SOC 2001: 325-335
1995
2	EE	S. Turgis, Nadine Azémard, Daniel Auvergne: Explicit evaluation of short circuit power dissipation for CMOS logic structures. ISLPD 1995: 129-134
1993
1	EE	Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne: Post-layout timing simulation of CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1170-1177 (1993)

Coauthor Index

1	M. Aline	[3] [5]
2	Daniel Auvergne	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [18] [20] [26]
3	Marc Belleville	[31]
4	Christian Bernard	[31]
5	Denis Deschacht	[1]
6	S. Engels	[19] [20] [21] [27]
7	A. Landrault	[12] [17] [23]
8	B. Lasbouygues	[11] [13] [16] [20] [22] [25] [28]
9	Philippe Maurine	[3] [4] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [30] [31]
10	Xavier Michel	[8] [9] [10] [14] [15] [18] [26]
11	V. Migairou	[21] [27]
12	Bettina Rebaud	[31]
13	Mustapha Rezzoug	[6]
14	Michel Robert	[1] [12] [31]
15	Lars J. Svensson	[29]
16	S. Turgis	[2]
17	Alexandre Verle	[9] [10] [14] [15] [17] [18] [23] [26]
18	Johan Vounckx	[24] [30]
19	Robin Wilson	[11] [13] [16] [19] [20] [21] [22] [25] [27] [28]
20	Zequin Wu	[27] [31]

Colors in the list of coauthors