| 2009 |
|---|
| 102 | EE | Pratik J. Shah,
Jiang Hu:
Impact of lithography-friendly circuit layout.
ACM Great Lakes Symposium on VLSI 2009: 385-388 |
| 2008 |
|---|
| 101 | EE | Yanfeng Wang,
Qiang Zhou,
Yici Cai,
Jiang Hu,
Xianlong Hong,
Jinian Bian:
Low power clock buffer planning methodology in F-D placement for large scale circuit design.
ASP-DAC 2008: 370-375 |
| 100 | EE | Sridhar Varadan,
Janet Meiling Wang,
Jiang Hu:
Handling partial correlations in yield prediction.
ASP-DAC 2008: 543-548 |
| 99 | EE | Nimay Shah,
Rupak Samanta,
Ming Zhang,
Jiang Hu,
Duncan Walker:
Built-In Proactive Tuning System for Circuit Aging Resilience.
DFT 2008: 96-104 |
| 98 | EE | Yifang Liu,
Rupesh S. Shelar,
Jiang Hu:
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization.
ICCAD 2008: 101-106 |
| 97 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu:
Gate planning during placement for gated clock network.
ICCD 2008: 128-133 |
| 96 | EE | Yifang Liu,
Jiang Hu,
Weiping Shi:
Multi-scenario buffer insertion in multi-core processor designs.
ISPD 2008: 15-22 |
| 95 | EE | Rupak Samanta,
Jiang Hu,
Peng Li:
Discrete buffer and wire sizing for link-based non-tree clock networks.
ISPD 2008: 175-181 |
| 94 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu:
Activity and register placement aware gated clock network design.
ISPD 2008: 182-189 |
| 93 | EE | Rupak Samanta,
Ganesh Venkataraman,
Nimay Shah,
Jiang Hu:
Elastic Timing Scheme for Energy-Efficient and Robust Performance.
ISQED 2008: 537-542 |
| 92 | EE | Xiaoji Ye,
Min Zhao,
Rajendran Panda,
Peng Li,
Jiang Hu:
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.
ISQED 2008: 627-632 |
| 91 | EE | Yifang Liu,
Jiang Hu,
Weiping Shi:
Buffering Interconnect for Multicore Processor Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(12): 2183-2196 (2008) |
| 90 | EE | Cheng Zhuo,
Jiang Hu,
Min Zhao,
Kangsheng Chen:
Power Grid Analysis and Optimization Using Algebraic Multigrid.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 738-751 (2008) |
| 89 | EE | Uday Padmanabhan,
Janet Meiling Wang,
Jiang Hu:
Robust Clock Tree Routing in the Presence of Process Variations.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(8): 1385-1397 (2008) |
| 88 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu:
Low Power Gated Clock Tree Driven Placement.
IEICE Transactions 91-A(2): 595-603 (2008) |
| 87 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu,
Bing Lu:
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm.
Integration 41(3): 426-438 (2008) |
| 2007 |
|---|
| 86 | EE | Bao Liu,
Andrew B. Kahng,
Xu Xu,
Jiang Hu,
Ganesh Venkataraman:
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield.
ASP-DAC 2007: 24-31 |
| 85 | EE | Jiang Hu,
Andi Winterboer,
Clifford Nass,
Johanna D. Moore,
Rebecca Illowsky:
Context & usability testing: user-modeled information presentation in easy and difficult driving conditions.
CHI 2007: 1343-1346 |
| 84 | EE | Shiyan Hu,
Mahesh Ketkar,
Jiang Hu:
Gate Sizing For Cell Library-Based Designs.
DAC 2007: 847-852 |
| 83 | EE | Shiyan Hu,
Jiang Hu:
Unified adaptivity optimization of clock and logic signals.
ICCAD 2007: 125-130 |
| 82 | EE | Cheng Zhuo,
Huafeng Zhang,
Rupak Samanta,
Jiang Hu,
Kangsheng Chen:
Modeling, optimization and control of rotary traveling-wave oscillator.
ICCAD 2007: 476-480 |
| 81 | EE | Xiaoji Ye,
Peng Li,
Min Zhao,
Rajendran Panda,
Jiang Hu:
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.
ICCAD 2007: 627-631 |
| 80 | EE | Shiyan Hu,
Jiang Hu:
Pattern sensitive placement for manufacturability.
ISPD 2007: 27-34 |
| 79 | EE | Zhanyuan Jiang,
Shiyan Hu,
Jiang Hu,
Weiping Shi:
An Efficient Algorithm for RLC Buffer Insertion.
ISQED 2007: 171-175 |
| 78 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu,
Bing Lu:
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture.
ISQED 2007: 299-304 |
| 77 | EE | Yang Liu,
Tong Zhang,
Jiang Hu:
Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders.
ISQED 2007: 749-754 |
| 76 | EE | Weixiang Shen,
Yici Cai,
Xianlong Hong,
Jiang Hu:
Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.
ISVLSI 2007: 383-388 |
| 75 | EE | Ganesh Venkataraman,
Jiang Hu:
A Placement Methodology for Robust Clocking.
VLSI Design 2007: 881-886 |
| 74 | EE | Shiyan Hu,
Qiuyang Li,
Jiang Hu,
Peng Li:
Utilizing Redundancy for Timing Critical Interconnect.
IEEE Trans. VLSI Syst. 15(10): 1067-1080 (2007) |
| 73 | EE | Ke Cao,
Jiang Hu,
Mosong Cheng:
Wire Sizing and Spacing for Lithographic Printability and Timing Optimization.
IEEE Trans. VLSI Syst. 15(12): 1332-1340 (2007) |
| 72 | EE | Ganesh Venkataraman,
Jiang Hu,
Frank Liu:
Integrated Placement and Skew Optimization for Rotary Clocking.
IEEE Trans. VLSI Syst. 15(2): 149-158 (2007) |
| 71 | EE | Shiyan Hu,
Charles J. Alpert,
Jiang Hu,
Shrirang K. Karandikar,
Zhuo Li,
Weiping Shi,
Chin-Ngai Sze:
Fast Algorithms for Slew-Constrained Minimum Cost Buffering.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2009-2022 (2007) |
| 70 | EE | Bor-Yiing Su,
Yao-Wen Chang,
Jiang Hu:
An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 719-733 (2007) |
| 69 | EE | Chin-Ngai Sze,
Charles J. Alpert,
Jiang Hu,
Weiping Shi:
Path-Based Buffer Insertion.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1346-1355 (2007) |
| 2006 |
|---|
| 68 | EE | Mike Brzozowski,
Kendra Carattini,
Scott R. Klemmer,
Patrick Mihelich,
Jiang Hu,
Andrew Y. Ng:
groupTime: preference based group scheduling.
CHI 2006: 1047-1056 |
| 67 | EE | Jamie Pearson,
Jiang Hu,
Holly P. Branigan,
Martin J. Pickering,
Clifford Nass:
Adaptive language behavior in HCI: how expectations and beliefs about a system affect users' word choice.
CHI 2006: 1177-1180 |
| 66 | EE | Shiyan Hu,
Charles J. Alpert,
Jiang Hu,
Shrirang K. Karandikar,
Zhuo Li,
Weiping Shi,
Cliff C. N. Sze:
Fast algorithms for slew constrained minimum cost buffering.
DAC 2006: 308-313 |
| 65 | EE | Shiyan Hu,
Qiuyang Li,
Jiang Hu,
Peng Li:
Steiner network construction for timing critical nets.
DAC 2006: 379-384 |
| 64 | EE | Ke Cao,
Sorin Dobre,
Jiang Hu:
Standard cell characterization considering lithography induced variations.
DAC 2006: 801-804 |
| 63 | EE | Ganesh Venkataraman,
Jiang Hu,
Frank Liu,
Cliff C. N. Sze:
Integrated placement and skew optimization for rotary clocking.
DATE 2006: 756-761 |
| 62 | EE | Min-Seok Kim,
Jiang Hu:
Associative skew clock routing for difficult instances.
DATE 2006: 762-767 |
| 61 | EE | Cheng Zhuo,
Jiang Hu,
Min Zhao,
Kangsheng Chen:
Fast decap allocation based on algebraic multigrid.
ICCAD 2006: 107-111 |
| 60 | EE | Zhanyuan Jiang,
Shiyan Hu,
Jiang Hu,
Zhuo Li,
Weiping Shi:
A new RLC buffer insertion algorithm.
ICCAD 2006: 553-557 |
| 59 | EE | Rupak Samanta,
Ganesh Venkataraman,
Jiang Hu:
Clock buffer polarity assignment for power noise reduction.
ICCAD 2006: 558-562 |
| 58 | EE | Ganesh Venkataraman,
Zhuo Feng,
Jiang Hu,
Peng Li:
Combinatorial algorithms for fast clock mesh optimization.
ICCAD 2006: 563-567 |
| 57 | EE | Weixiang Shen,
Yici Cai,
Jiang Hu,
Xianlong Hong,
Bing Lu:
High performance clock routing in X-architecture.
ISCAS 2006 |
| 56 | EE | Uday Padmanabhan,
Janet Meiling Wang,
Jiang Hu:
Statistical clock tree routing for robustness to process variations.
ISPD 2006: 149-156 |
| 55 | EE | Bor-Yiing Su,
Yao-Wen Chang,
Jiang Hu:
An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles.
ISPD 2006: 56-63 |
| 54 | EE | Cheng Zhuo,
Jiang Hu,
Kangsheng Chen:
An Improved AMG-based Method for Fast Power Grid Analysis.
ISQED 2006: 290-295 |
| 53 | EE | Zhuo Feng,
Peng Li,
Jiang Hu:
Efficient Model Update for General Link-Insertion Networks.
ISQED 2006: 43-50 |
| 52 | EE | Di Wu,
Jiang Hu,
Rabi N. Mahapatra:
Antenna Avoidance in Layer Assignment.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 734-738 (2006) |
| 51 | EE | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1140-1145 (2006) |
| 50 | EE | Anand Rajaram,
Jiang Hu,
Rabi N. Mahapatra:
Reducing clock skew variability via crosslinks.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1176-1182 (2006) |
| 49 | EE | Anand Rajaram,
Bing Lu,
Jiang Hu,
Rabi N. Mahapatra,
Wei Guo:
Analytical bound for unwanted clock skew due to wire width variation.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1869-1876 (2006) |
| 2005 |
|---|
| 48 | EE | Di Wu,
Jiang Hu,
Min Zhao,
Rabi N. Mahapatra:
Timing driven track routing considering coupling capacitance.
ASP-DAC 2005: 1156-1159 |
| 47 | EE | Zhuo Li,
Cliff C. N. Sze,
Charles J. Alpert,
Jiang Hu,
Weiping Shi:
Making fast buffer insertion even faster via approximation techniques.
ASP-DAC 2005: 13-18 |
| 46 | EE | Ke Cao,
Puneet Dhawan,
Jiang Hu:
Library cell layout with Alt-PSM compliance and composability.
ASP-DAC 2005: 216-219 |
| 45 | EE | Yongqiang Lu,
Cliff C. N. Sze,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Liang Huang,
Jiang Hu:
Register placement for low power clock network.
ASP-DAC 2005: 588-593 |
| 44 | EE | Ganesh Venkataraman,
Cliff C. N. Sze,
Jiang Hu:
Skew scheduling and clock routing for improved tolerance to process variations.
ASP-DAC 2005: 594-599 |
| 43 | EE | Liang Huang,
Yici Cai,
Qiang Zhou,
Xianlong Hong,
Jiang Hu,
Yongqiang Lu:
Clock network minimization methodology based on incremental placement.
ASP-DAC 2005: 99-102 |
| 42 | EE | Yongqiang Lu,
Cliff C. N. Sze,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Liang Huang,
Jiang Hu:
Navigating registers in placement for clock network minimization.
DAC 2005: 176-181 |
| 41 | EE | Cliff C. N. Sze,
Charles J. Alpert,
Jiang Hu,
Weiping Shi:
Path based buffer insertion.
DAC 2005: 509-514 |
| 40 | | Di Wu,
Ganesh Venkataraman,
Jiang Hu,
Quiyang Li,
Rabi N. Mahapatra:
DiCER: distributed and cost-effective redundancy for variation tolerance.
ICCAD 2005: 393-397 |
| 39 | | Ganesh Venkataraman,
Nikhil Jayakumar,
Jiang Hu,
Peng Li,
Sunil P. Khatri,
Anand Rajaram,
Patrick McGuinness,
Charles J. Alpert:
Practical techniques to reduce skew and its variations in buffered clock networks.
ICCAD 2005: 592-596 |
| 38 | EE | QianYing Wang,
Clifford Nass,
Jiang Hu:
Natural Language Query vs. Keyword Search: Effects of Task Complexity on Search Performance, Participant Perceptions, and Preferences.
INTERACT 2005: 106-116 |
| 37 | EE | Jiang Hu,
Mike Brzozowski:
Preference-Based Group Scheduling.
INTERACT 2005: 990-993 |
| 36 | EE | Di Wu,
Jiang Hu,
Rabi N. Mahapatra:
Coupling aware timing optimization and antenna avoidance in layer assignment.
ISPD 2005: 20-27 |
| 35 | EE | Anand Rajaram,
David Z. Pan,
Jiang Hu:
Improved algorithms for link-based non-tree clock networks for skew variability reduction.
ISPD 2005: 55-62 |
| 34 | | QianYing Wang,
Jiang Hu,
Clifford Nass:
Natural Language Interface Put in Perspective: Interaction of Search Method and Task Complexity.
NLUCS 2005: 3-12 |
| 33 | EE | Rishi Chaturvedi,
Jiang Hu:
An efficient merging scheme for prescribed skew clock routing.
IEEE Trans. VLSI Syst. 13(6): 750-754 (2005) |
| 32 | EE | Yongqiang Lu,
Chin-Ngai Sze,
Xianlong Hong,
Qiang Zhou,
Yici Cai,
Liang Huang,
Jiang Hu:
Navigating Register Placement for Low Power Clock Network Design.
IEICE Transactions 88-A(12): 3405-3411 (2005) |
| 2004 |
|---|
| 31 | EE | Di Wu,
Jiang Hu,
Rabi N. Mahapatra,
Min Zhao:
Layer assignment for crosstalk risk minimization.
ASP-DAC 2004: 159-162 |
| 30 | EE | Cliff C. N. Sze,
Jiang Hu,
Charles J. Alpert:
A place and route aware buffered Steiner tree construction.
ASP-DAC 2004: 355-360 |
| 29 | EE | Anand Rajaram,
Jiang Hu,
Rabi N. Mahapatra:
Reducing clock skew variability via cross links.
DAC 2004: 18-23 |
| 28 | EE | Charles J. Alpert,
Milos Hrkic,
Jiang Hu,
Stephen T. Quay:
Fast and flexible buffer trees that navigate the physical layout environment.
DAC 2004: 24-29 |
| 27 | EE | V. Seth,
Min Zhao,
Jiang Hu:
Exploiting level sensitive latches in wire pipelining.
ICCAD 2004: 283-290 |
| 26 | EE | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Cliff C. N. Sze:
Accurate estimation of global buffer delay within a floorplan.
ICCAD 2004: 706-711 |
| 25 | EE | Rishi Chaturvedi,
Jiang Hu:
Buffered Clock Tree for High Quality IC Design.
ISQED 2004: 381-386 |
| 24 | EE | Charles J. Alpert,
Chris C. N. Chu,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Chandramouli V. Kashyap,
Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 136-141 (2004) |
| 23 | EE | Haihua Su,
Jiang Hu,
Sachin S. Sapatnekar,
Sani R. Nassif:
A methodology for the simultaneous design of supply and signal networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1614-1624 (2004) |
| 22 | EE | Charles J. Alpert,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Stephen T. Quay,
Cliff C. N. Sze:
Porosity-aware buffered Steiner tree construction.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 517-526 (2004) |
| 2003 |
|---|
| 21 | EE | Anand Rajaram,
Bing Lu,
Wei Guo,
Rabi N. Mahapatra,
Jiang Hu:
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation.
ICCAD 2003: 401-407 |
| 20 | EE | Rishi Chaturvedi,
Jiang Hu:
A Simple Yet Effective Merging Scheme for Prescribed-Skew Clock Routing.
ICCD 2003: 282- |
| 19 | EE | Charles J. Alpert,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Stephen T. Quay:
Porosity aware buffered steiner tree construction.
ISPD 2003: 158-165 |
| 18 | EE | Bing Lu,
Jiang Hu,
Gary Ellis,
Haihua Su:
Process variation aware clock tree routing.
ISPD 2003: 174-181 |
| 17 | EE | Jiang Hu,
Charles J. Alpert,
Stephen T. Quay,
Gopal Gandham:
Buffer insertion with adaptive blockage avoidance.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 492-498 (2003) |
| 16 | EE | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Paul Villarrubia:
A practical methodology for early buffer and wire resource allocation.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 573-583 (2003) |
| 2002 |
|---|
| 15 | EE | Haihua Su,
Jiang Hu,
Sachin S. Sapatnekar,
Sani R. Nassif:
Congestion-driven codesign of power and signal networks.
DAC 2002: 64-69 |
| 14 | EE | Charles J. Alpert,
Chris C. N. Chu,
Gopal Gandham,
Milos Hrkic,
Jiang Hu,
Chandramouli V. Kashyap,
Stephen T. Quay:
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
ISPD 2002: 104-109 |
| 13 | EE | Jiang Hu,
Charles J. Alpert,
Stephen T. Quay,
Gopal Gandham:
Buffer insertion with adaptive blockage avoidance.
ISPD 2002: 92-97 |
| 12 | EE | Jiang Hu,
Sachin S. Sapatnekar:
A timing-constrained simultaneous global routing algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(9): 1025-1036 (2002) |
| 2001 |
|---|
| 11 | EE | Charles J. Alpert,
Jiang Hu,
Sachin S. Sapatnekar,
Paul Villarrubia:
A Practical Methodology for Early Buffer and Wire Resource Allocation.
DAC 2001: 189-194 |
| 10 | | Jiang Hu,
Sachin S. Sapatnekar:
Performance Driven Global Routing Through Gradual Refinement.
ICCD 2001: 481-483 |
| 9 | EE | Charles J. Alpert,
Gopal Gandham,
Jiang Hu,
José Luis Neves,
Stephen T. Quay,
Sachin S. Sapatnekar:
Steiner tree optimization for buffers. Blockages and bays.
ISCAS (5) 2001: 399-402 |
| 8 | EE | Charles J. Alpert,
Milos Hrkic,
Jiang Hu,
Andrew B. Kahng,
John Lillis,
Bao Liu,
Stephen T. Quay,
Sachin S. Sapatnekar,
A. J. Sullivan,
Paul Villarrubia:
Buffered Steiner trees for difficult instances.
ISPD 2001: 4-9 |
| 7 | EE | Charles J. Alpert,
Gopal Gandham,
Jiang Hu,
José Luis Neves,
Stephen T. Quay,
Sachin S. Sapatnekar:
Steiner tree optimization for buffers, blockages, and bays.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 556-562 (2001) |
| 6 | EE | Jiang Hu,
Sachin S. Sapatnekar:
A survey on multi-net global routing for integrated circuits.
Integration 31(1): 1-49 (2001) |
| 2000 |
|---|
| 5 | | Jiang Hu,
Sachin S. Sapatnekar:
A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets.
ICCAD 2000: 99-103 |
| 4 | EE | Jiang Hu,
Sachin S. Sapatnekar:
Algorithms for non-Hanan-based optimization for VLSI interconnectunder a higher-order AWE model.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(4): 446-458 (2000) |
| 1999 |
|---|
| 3 | EE | Jiang Hu,
Sachin S. Sapatnekar:
FAR-DS: Full-Plane AWE Routing with Driver Sizing.
DAC 1999: 84-89 |
| 2 | EE | Jiang Hu,
Sachin S. Sapatnekar:
Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model.
ISPD 1999: 133-138 |
| 1 | EE | Huibo Hou,
Jiang Hu,
Sachin S. Sapatnekar:
Non-Hanan routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 436-444 (1999) |
