Kaviraj Chopra

2008
19	EE	Brian Cline, Kaviraj Chopra, David Blaauw, Andres Torres, Savithri Sundareswaran: Transistor-Specific Delay Modeling for SSTA. DATE 2008: 592-597
18	EE	Kaviraj Chopra, Cheng Zhuo, David Blaauw, Dennis Sylvester: A statistical approach for full-chip gate-oxide reliability analysis. ICCAD 2008: 698-705
17	EE	Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw: A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 272-285 (2008)
16	EE	David Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer: Statistical Timing Analysis: From Basic Principles to State of the Art. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 589-607 (2008)
2007
15	EE	Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer: Top-k Aggressors Sets in Delay Noise Analysis. DAC 2007: 174-179
14	EE	Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada: Victim alignment in crosstalk aware timing analysis. ICCAD 2007: 698-704
13	EE	Aseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing CoRR abs/0710.4697: (2007)
12	EE	Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester: Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 468-479 (2007)
2006
11	EE	Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester: An efficient static algorithm for computing the soft error rates of combinational circuits. DATE 2006: 164-169
10	EE	Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester: A new statistical max operation for propagating skewness in statistical timing analysis. ICCAD 2006: 237-243
9	EE	Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao: Analysis and modeling of CD variation for statistical static timing. ICCAD 2006: 60-66
8	EE	Kaviraj Chopra, Sarma B. K. Vrudhula: Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2820-2832 (2006)
2005
7	EE	Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov: Circuit optimization using statistical static timing analysis. DAC 2005: 321-324
6	EE	David Blaauw, Kaviraj Chopra: CAD tools for variation tolerance. DAC 2005: 766
5	EE	Aseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing. DATE 2005: 400-405
4		Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester: Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. ICCAD 2005: 1023-1028
2004
3	EE	Kaviraj Chopra, Sarma B. K. Vrudhula: Implicit pseudo boolean enumeration algorithms for input vector control. DAC 2004: 767-772
2	EE	Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan: A Framework for Battery-Aware Sensor Management. DATE 2004: 962-967
1	EE	Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj: Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. VLSI Design 2004: 240-

Coauthor Index

1	Aseem Agarwal	[5] [7] [13]
2	Murat R. Becer	[14] [15]
3	Sarvesh Bhardwaj	[1]
4	David Blaauw (David T. Blaauw)	[4] [5] [6] [7] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19]
5	Yu Cao	[9]
6	Brian Cline	[9] [19]
7	Sridhar Dasika	[2]
8	Ravikishore Gandikota	[14] [15]
9	Joao Geada	[14]
10	Rajeev R. Rao	[11] [12]
11	Louis Scheffer	[16]
12	Saumil Shah	[4] [17]
13	R. Srinivasan	[2]
14	Ashish Srivastava	[4] [16] [17]
15	Savithri Sundareswaran	[19]
16	Dennis Sylvester	[4] [10] [11] [12] [14] [15] [17] [18]
17	Andres Torres	[19]
18	Sarma B. K. Vrudhula	[1] [2] [3] [8]
19	Bo Zhai	[10]
20	Cheng Zhuo	[18]
21	Vladimir Zolotov	[7]