Geert Van der Plas

2008
18	EE	Pierluigi Nuzzo, Claudio Nani, Sergio Saponara, Luca Fanucci, Geert Van der Plas: Mixed-Signal Design Space Exploration of Time-Interleaved A/D Converters for Ultra-Wide Band Applications. DATE 2008: 1390-1393
2007
17	EE	Stephane Bronckers, Charlotte Soens, Geert Van der Plas, Gerd Vandersteen, Yves Rolain: Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO's. DATE 2007: 1520-1525
16	EE	Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Scalable Gate-Level Models for Power and Timing Analysis. ISCAS 2007: 2938-2941
15	EE	Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay: Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance CoRR abs/0710.4723: (2007)
2006
14	EE	Pierluigi Nuzzo, Geert Van der Plas, Fernando De Bernardinis, Liesbet Van der Perre, Bert Gyselinckx, Pierangelo Terreni: A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18mum CMOS with 5.8GHz ERBW. DAC 2006: 873-878
13	EE	Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. VLSI Syst. 14(1): 23-33 (2006)
12	EE	Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1146-1154 (2006)
2005
11	EE	Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay: Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. DATE 2005: 270-275
10	EE	Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 65-76 (2005)
2004
9	EE	Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC 2004: 854-859
8	EE	Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE 2004: 88-93
2002
7	EE	Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen: CYCLONE: automated design and layout of RF LC-oscillators. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1161-1170 (2002)
6	EE	Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen: A layout synthesis methodology for array-type analog blocks. IEEE Trans. on CAD of Integrated Circuits and Systems 21(6): 645-661 (2002)
2001
5	EE	Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen: A Layout-Aware Synthesis Methodology for RF Circuits. ICCAD 2001: 358-
4	EE	Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts: AMGIE-A synthesis environment for CMOS analog integrated circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 20(9): 1037-1058 (2001)
2000
3	EE	Carl De Ranter, B. De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen: CYCLONE: automated design and layout of RF LC-oscillators. DAC 2000: 11-14
2	EE	Geert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen: Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. DAC 2000: 452-457
1997
1	EE	Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen: Automated test pattern generation for analog integrated circuits. VTS 1997: 296-301

Coauthor Index

1	Mustafa Badaroglu	[8] [9] [10] [12] [13] [16]
2	Fernando De Bernardinis	[14]
3	Antal van den Bosch	[2]
4	Stephane Bronckers	[17]
5	Walter Daems	[2]
6	Geert Debyser	[4]
7	Petr Dobrovolný	[9]
8	Stéphane Donnay	[8] [9] [10] [11] [12] [13] [15] [16]
9	Luca Fanucci	[18]
10	Georges G. E. Gielen	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [12] [13] [16]
11	Bert Gyselinckx	[14]
12	Koen Lampaert	[4]
13	Domine Leenaerts	[4]
14	Francky Leyn	[4]
15	Hugo De Man	[8] [9] [10] [12] [13] [16]
16	B. De Muer	[3]
17	Claudio Nani	[18]
18	Pierluigi Nuzzo	[14] [18]
19	Liesbet Van der Perre	[14]
20	Carl De Ranter	[3] [7]
21	Yves Rolain	[17]
22	Willy M. C. Sansen	[2] [3] [4] [5] [6] [7]
23	Sergio Saponara	[18]
24	Charlotte Soens	[11] [15] [17]
25	Michiel Steyaert	[3] [5] [7]
26	Pierangelo Terreni	[14]
27	Kris Tiri	[12]
28	Peter J. Vancorenland	[3] [5]
29	Jan Vandenbussche	[2] [4] [6]
30	Gerd Vandersteen	[9] [17]
31	Ingrid Verbauwhede	[12]
32	Wim Verhaegen	[1]
33	Petar Veselinovic	[4]
34	Piet Wambacq	[8] [9] [10] [11] [12] [13] [15] [16]