David T. Blaauw
List of publications from the DBLP Bibliography Server - FAQ
2008 | ||
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201 | EE | Vineeth Veetil, Dennis Sylvester, David Blaauw: Efficient Monte Carlo based incremental statistical timing analysis. DAC 2008: 676-681 |
200 | EE | Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Leakage power reduction using stress-enhanced layouts. DAC 2008: 912-917 |
199 | EE | Ravikishore Gandikota, David Blaauw, Dennis Sylvester: Modeling crosstalk in statistical static timing analysis. DAC 2008: 974-979 |
198 | EE | Brian Cline, Kaviraj Chopra, David Blaauw, Andres Torres, Savithri Sundareswaran: Transistor-Specific Delay Modeling for SSTA. DATE 2008: 592-597 |
197 | EE | Jae-sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw: On the decreasing significance of large standard cells in technology mapping. ICCAD 2008: 116-121 |
196 | EE | Brian Cline, Vivek Joshi, Dennis Sylvester, David Blaauw: STEEL: a technique for stress-enhanced standard cell library design. ICCAD 2008: 691-697 |
195 | EE | Kaviraj Chopra, Cheng Zhuo, David Blaauw, Dennis Sylvester: A statistical approach for full-chip gate-oxide reliability analysis. ICCAD 2008: 698-705 |
194 | EE | Yu-Shiang Lin, Scott Hanson, Fabio Albano, Carlos Tokunaga, Razi-Ul Haque, Kensall Wise, Ann Marie Sastry, David Blaauw, Dennis Sylvester: Low-voltage circuit design for widespread sensing applications. ISCAS 2008: 2558-2561 |
193 | EE | Cheng Zhuo, David Blaauw, Dennis Sylvester: Variation-aware gate sizing and clustering for post-silicon optimized circuits. ISLPED 2008: 105-110 |
192 | EE | Mingoo Seok, Dennis Sylvester, David Blaauw: Optimal technology selection for minimizing energy and variability in low voltage applications. ISLPED 2008: 9-14 |
191 | EE | Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Stress aware layout optimization. ISPD 2008: 168-174 |
190 | EE | Eric Karl, Dennis Sylvester, David Blaauw: Analysis of System-Level Reliability Factors and Implications on Real-Time Monitoring Methods for Oxide Breakdown Device Failures. ISQED 2008: 391-395 |
189 | EE | Vineeth Veetil, Dennis Sylvester, David Blaauw: Fast and Accurate Waveform Analysis with Current Source Models. ISQED 2008: 53-56 |
188 | EE | Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David Blaauw, Dennis Sylvester, Krisztián Flautner: Reconfigurable energy efficient near threshold cache architectures. MICRO 2008: 459-470 |
187 | EE | Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Multi-Mechanism Reliability Modeling and Management in Dynamic Systems. IEEE Trans. VLSI Syst. 16(4): 476-487 (2008) |
186 | EE | Prashant Singh, Jae-sun Seo, David Blaauw, Dennis Sylvester: Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect. IEEE Trans. VLSI Syst. 16(6): 673-677 (2008) |
185 | EE | Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw: A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 272-285 (2008) |
184 | EE | Sarvesh H. Kulkarni, D. M. Sylvester, David T. Blaauw: Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3): 481-494 (2008) |
183 | EE | David Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer: Statistical Timing Analysis: From Basic Principles to State of the Art. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 589-607 (2008) |
2007 | ||
182 | EE | Sanjay Pant, David Blaauw: Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks. ASP-DAC 2007: 757-762 |
181 | EE | Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer: Top-k Aggressors Sets in Delay Noise Analysis. DAC 2007: 174-179 |
180 | EE | Mingoo Seok, Scott Hanson, Dennis Sylvester, David Blaauw: Analysis and Optimization of Sleep Modes in Subthreshold Circuit Design. DAC 2007: 694-699 |
179 | EE | Scott Hanson, Mingoo Seok, Dennis Sylvester, David Blaauw: Nanometer Device Scaling in Subthreshold Circuits. DAC 2007: 700-705 |
178 | EE | Gregory K. Chen, David Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim: Yield-driven near-threshold SRAM design. ICCAD 2007: 660-666 |
177 | EE | Vivek Joshi, David Blaauw, Dennis Sylvester: Soft-edge flip-flops for improved timing yield: design and optimization. ICCAD 2007: 667-673 |
176 | EE | Ravikishore Gandikota, Kaviraj Chopra, David Blaauw, Dennis Sylvester, Murat R. Becer, Joao Geada: Victim alignment in crosstalk aware timing analysis. ICCAD 2007: 698-704 |
175 | EE | Bo Zhai, Ronald G. Dreslinski, David Blaauw, Trevor N. Mudge, Dennis Sylvester: Energy efficient near-threshold chip multi-processing. ISLPED 2007: 32-37 |
174 | EE | Jae-sun Seo, Dennis Sylvester, David Blaauw, Himanshu Kaul, Ram Krishnamurthy: A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED 2007: 68-73 |
173 | EE | Jae-sun Seo, Prashant Singh, Dennis Sylvester, David Blaauw: Self-Time Regenerators for High-Speed and Low-Power Interconnect. ISQED 2007: 621-626 |
172 | EE | Mini Nanua, David Blaauw: Investigating Crosstalk in Sub-Threshold Circuits. ISQED 2007: 639-646 |
171 | EE | Ronald G. Dreslinski, Bo Zhai, Trevor N. Mudge, David Blaauw, Dennis Sylvester: An Energy Efficient Parallel Architecture Using Near Threshold Operation. PACT 2007: 175-188 |
170 | EE | Mini Nanua, David Blaauw: Crosstalk Waveform Modeling Using Wave Fitting. PATMOS 2007: 211-221 |
169 | EE | Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction CoRR abs/0710.4679: (2007) |
168 | EE | Aseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing CoRR abs/0710.4697: (2007) |
167 | EE | Sanjay Pant, Eli Chiprout, David Blaauw: Power Grid Physics and Implications for CAD. IEEE Design & Test of Computers 24(3): 246-254 (2007) |
166 | EE | Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester: Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 468-479 (2007) |
2006 | ||
165 | EE | Eric Karl, David Blaauw, Dennis Sylvester, Trevor N. Mudge: Reliability modeling and management in dynamic microprocessor-based systems. DAC 2006: 1057-1060 |
164 | EE | Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Dennis Sylvester: An efficient static algorithm for computing the soft error rates of combinational circuits. DATE 2006: 164-169 |
163 | EE | Kaviraj Chopra, Bo Zhai, David Blaauw, Dennis Sylvester: A new statistical max operation for propagating skewness in statistical timing analysis. ICCAD 2006: 237-243 |
162 | EE | Sarvesh H. Kulkarni, Dennis Sylvester, David Blaauw: A statistical framework for post-silicon tuning through body bias clustering. ICCAD 2006: 39-46 |
161 | EE | Rajeev R. Rao, David Blaauw, Dennis Sylvester: Soft error reduction in combinational logic using gate resizing and flipflop selection. ICCAD 2006: 502-509 |
160 | EE | Brian Cline, Kaviraj Chopra, David Blaauw, Yu Cao: Analysis and modeling of CD variation for statistical static timing. ICCAD 2006: 60-66 |
159 | EE | Sanjay Pant, David Blaauw: An Active Decoupling Capacitance Circuit for Inductive Noise Suppression in Power Supply Networks. ICCD 2006 |
158 | EE | David Blaauw, Bo Zhai: Energy efficient design for subthreshold supply voltage operation. ISCAS 2006 |
157 | EE | Scott Hanson, Dennis Sylvester, David Blaauw: A new technique for jointly optimizing gate sizing and supply voltage in ultra-low energy circuits. ISLPED 2006: 338-341 |
156 | EE | Scott Hanson, Bo Zhai, David Blaauw, Dennis Sylvester, Andres Bryant, Xinlin Wang: Energy optimality and variability in subthreshold design. ISLPED 2006: 363-365 |
155 | EE | Vivek Joshi, Rajeev R. Rao, David Blaauw, Dennis Sylvester: Logic SER Reduction through Flipflop Redesign. ISQED 2006: 611-616 |
154 | EE | Mini Nanua, David Blaauw: Receiver Modeling for Static Functional Crosstalk Analysis. PATMOS 2006: 329-339 |
153 | EE | Scott Hanson, Bo Zhai, Kerry Bernstein, David Blaauw, Andres Bryant, Leland Chang, Koushik K. Das, Wilfried Haensch, Edward J. Nowak, Dennis Sylvester: Ultralow-voltage, minimum-energy CMOS. IBM Journal of Research and Development 50(4-5): 469-490 (2006) |
152 | EE | Dennis Sylvester, David Blaauw, Eric Karl: ElastIC: An Adaptive Self-Healing Architecture for Unpredictable Silicon. IEEE Design & Test of Computers 23(6): 484-490 (2006) |
151 | EE | Dongwoo Lee, David Blaauw, Dennis Sylvester: Runtime Leakage Minimization Through Probability-Aware Optimization. IEEE Trans. VLSI Syst. 14(10): 1075-1088 (2006) |
150 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 892-901 (2006) |
149 | EE | Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw: Statistical interconnect metrics for physical-design optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1273-1288 (2006) |
148 | EE | Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Analytical yield prediction considering leakage/performance correlation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1685-1695 (2006) |
2005 | ||
147 | EE | Amit Jain, David Blaauw: Slack borrowing in flip-flop based sequential circuits. ACM Great Lakes Symposium on VLSI 2005: 96-101 |
146 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan: Achieving continuous VT performance in a dual VT process. ASP-DAC 2005: 393-398 |
145 | EE | David Blaauw, Anirudh Devgan, Farid N. Najm: Leakage power: trends, analysis and avoidance. ASP-DAC 2005 |
144 | EE | Todd M. Austin, Valeria Bertacco, David Blaauw, Trevor N. Mudge: Opportunities and challenges for better than worst-case design. ASP-DAC 2005: 2-7 |
143 | EE | Dongwoo Lee, David Blaauw, Dennis Sylvester: Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment. ASP-DAC 2005: 399-404 |
142 | EE | Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw: Statistical modeling of cross-coupling effects in VLSI interconnects. ASP-DAC 2005: 503-506 |
141 | EE | Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David Blaauw: A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution. CASES 2005: 249-256 |
140 | EE | Aseem Agarwal, Kaviraj Chopra, David Blaauw, Vladimir Zolotov: Circuit optimization using statistical static timing analysis. DAC 2005: 321-324 |
139 | EE | Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540 |
138 | EE | David Blaauw, Kaviraj Chopra: CAD tools for variation tolerance. DAC 2005: 766 |
137 | EE | Aseem Agarwal, Kaviraj Chopra, David Blaauw: Statistical Timing Based Optimization using Gate Sizing. DATE 2005: 400-405 |
136 | EE | Himanshu Kaul, Dennis Sylvester, David Blaauw, Trevor N. Mudge, Todd M. Austin: DVS for On-Chip Bus Designs Based on Timing Error Correction. DATE 2005: 80-85 |
135 | Kaviraj Chopra, Saumil Shah, Ashish Srivastava, David Blaauw, Dennis Sylvester: Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. ICCAD 2005: 1023-1028 | |
134 | Sanjay Pant, David Blaauw: Static timing analysis considering power supply variations. ICCAD 2005: 365-371 | |
133 | Saumil Shah, Ashish Srivastava, Dushyant Sharma, Dennis Sylvester, David Blaauw, Vladimir Zolotov: Discrete Vt assignment and gate sizing using a self-snapping continuous formulation. ICCAD 2005: 705-712 | |
132 | Amit Jain, David Blaauw, Vladimir Zolotov: Accurate delay computation for noisy waveform shapes. ICCAD 2005: 947-953 | |
131 | EE | Leyla Nazhandali, Bo Zhai, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Sanjay Pant, Todd M. Austin, David Blaauw: Energy Optimization of Subthreshold-Voltage Sensor Network Processors. ISCA 2005: 197-207 |
130 | EE | Eric Karl, Dennis Sylvester, David Blaauw: Timing error correction techniques for voltage-scalable on-chip memories. ISCAS (4) 2005: 3563-3566 |
129 | EE | Bo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester: Analysis and mitigation of variability in subthreshold design. ISLPED 2005: 20-25 |
128 | EE | Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif: An efficient surface-based low-power buffer insertion algorithm. ISPD 2005: 86-93 |
127 | EE | Mini Nanua, David Blaauw, Chanhee Oh: Leakage Current Modeling in PD SOI Circuits. ISQED 2005: 113-117 |
126 | EE | Harmander Deogun, Dennis Sylvester, David Blaauw: Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate. ISQED 2005: 175-180 |
125 | EE | David Roberts, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Error Analysis for the Support of Robust Voltage Scaling. ISQED 2005: 65-70 |
124 | EE | Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan: Modeling and Analysis of Parametric Yield under Power and Performance Constraints. IEEE Design & Test of Computers 22(4): 376-385 (2005) |
123 | EE | Nam Sung Kim, David Blaauw, Trevor N. Mudge: Quantitative analysis and optimization techniques for on-chip cache leakage power. IEEE Trans. VLSI Syst. 13(10): 1147-1156 (2005) |
122 | EE | Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner: The limit of dynamic voltage scaling and insomniac dynamic voltage scaling. IEEE Trans. VLSI Syst. 13(11): 1239-1252 (2005) |
121 | EE | Rajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester: Bus encoding for total power reduction using a leakage-aware buffer configuration. IEEE Trans. VLSI Syst. 13(12): 1376-1383 (2005) |
120 | EE | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Probability distribution of signal arrival times using Bayesian networks. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1784-1794 (2005) |
119 | EE | Dongwoo Lee, David Blaauw, Dennis Sylvester: Static leakage reduction through simultaneous V/sub t//T/sub ox/ and state assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 24(7): 1014-1029 (2005) |
2004 | ||
118 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. ASP-DAC 2004: 858-864 |
117 | EE | Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: A stochastic approach To power grid analysis. DAC 2004: 171-176 |
116 | EE | Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David Blaauw, Trevor N. Mudge: Circuit-aware architectural simulation. DAC 2004: 305-310 |
115 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384 |
114 | EE | Rajeev R. Rao, Anirudh Devgan, David Blaauw, Dennis Sylvester: Parametric yield estimation considering leakage variability. DAC 2004: 442-447 |
113 | EE | Aseem Agarwal, Florentin Dartu, David Blaauw: Statistical gate delay model considering multiple input switching. DAC 2004: 658-663 |
112 | EE | Dongwoo Lee, Vladimir Zolotov, David Blaauw: Static timing analysis using backward signal propagation. DAC 2004: 664-669 |
111 | EE | Ashish Srivastava, Dennis Sylvester, David Blaauw: Statistical optimization of leakage power considering process variations using dual-Vth and sizing. DAC 2004: 773-778 |
110 | EE | Harmander Deogun, Rajeev R. Rao, Dennis Sylvester, David Blaauw: Leakage-and crosstalk-aware bus encoding for total power reduction. DAC 2004: 779-782 |
109 | EE | Ashish Srivastava, Dennis Sylvester, David Blaauw: Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. DAC 2004: 783-787 |
108 | EE | Bo Zhai, David Blaauw, Dennis Sylvester, Krisztián Flautner: Theoretical and practical limits of dynamic voltage scaling. DAC 2004: 868-873 |
107 | EE | Dongwoo Lee, Harmander Deogun, David Blaauw, Dennis Sylvester: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization. DATE 2004: 494-499 |
106 | EE | Ashish Srivastava, Dennis Sylvester, David Blaauw: Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. DATE 2004: 718-719 |
105 | EE | Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David Blaauw, Trevor N. Mudge: Reducing pipeline energy demands with local DVS and dynamic retiming. ISLPED 2004: 319-324 |
104 | EE | Woo Hyung Lee, Sanjay Pant, David Blaauw: Analysis and Reduction of On-Chip Inductance Effects in Power Supply Grids. ISQED 2004: 131-136 |
103 | EE | Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner: Making Typical Silicon Matter with Razor. IEEE Computer 37(3): 57-65 (2004) |
102 | EE | Todd M. Austin, David Blaauw, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Wayne Wolf: Mobile Supercomputers. IEEE Computer 37(5): 81-83 (2004) |
101 | EE | Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner: Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro 24(6): 10-20 (2004) |
100 | Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 131-139 (2004) | |
99 | Dongwoo Lee, David Blaauw, Dennis Sylvester: Gate oxide leakage current analysis and reduction for VLSI circuits. IEEE Trans. VLSI Syst. 12(2): 155-166 (2004) | |
98 | Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Trans. VLSI Syst. 12(2): 167-184 (2004) | |
97 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driver output model for on-chip RLC transmission lines. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 128-136 (2004) |
96 | EE | Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Postroute gate sizing for crosstalk noise reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1670-1677 (2004) |
95 | EE | Aseem Agarwal, Vladimir Zolotov, David Blaauw: Statistical clock skew analysis considering intradie-process variations. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1231-1242 (2004) |
94 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1346-1354 (2004) |
2003 | ||
93 | EE | Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang: Reshaping EDA for power. DAC 2003: 15 |
92 | EE | Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Analysis and minimization techniques for total leakage considering gate oxide leakage. DAC 2003: 175-180 |
91 | EE | Dongwoo Lee, David Blaauw: Static leakage reduction through simultaneous threshold voltage and state assignment. DAC 2003: 191-194 |
90 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Computation and Refinement of Statistical Bounds on Circuit Delay. DAC 2003: 348-353 |
89 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: An effective capacitance based driver output model for on-chip RLC interconnects. DAC 2003: 376-381 |
88 | EE | Bhavana Thudi, David Blaauw: Non-iterative switching window computation for delay-noise. DAC 2003: 390-395 |
87 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: Simple metrics for slew rate of RC circuits based on two circuit moments. DAC 2003: 950-953 |
86 | EE | Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-route gate sizing for crosstalk noise reduction. DAC 2003: 954-957 |
85 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical Timing Analysis Using Bounds. DATE 2003: 10062-10067 |
84 | EE | D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel: SOI Transistor Model for Fast Transient Simulation. ICCAD 2003: 120128 |
83 | EE | Sanjay Pant, David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda: Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD 2003: 184-192 |
82 | EE | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: AU: Timing Analysis Under Uncertainty. ICCAD 2003: 615-620 |
81 | EE | Nam Sung Kim, David Blaauw, Trevor N. Mudge: Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches. ICCAD 2003: 627-632 |
80 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations. ICCAD 2003: 900-907 |
79 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov: Statistical Clock Skew Analysis Considering Intra-Die Process Variations. ICCAD 2003: 914-921 |
78 | EE | Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester: Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264- |
77 | EE | Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) 2003: 668-671 |
76 | EE | Rajeev R. Rao, Ashish Srivastava, David Blaauw, Dennis Sylvester: Statistical estimation of leakage current considering inter- and intra-die process variation. ISLPED 2003: 84-89 |
75 | EE | Murat R. Becer, David Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj: Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED 2003: 171-176 |
74 | EE | Dongwoo Lee, Wesley Kwong, David Blaauw, Dennis Sylvester: Simultaneous Subthreshold and Gate-Oxide Tunneling Leakage Current Analysis in Nanometer CMOS Design. ISQED 2003: 287-292 |
73 | EE | Chanhee Oh, David Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta: Static Electromigration Analysis for Signal Interconnects. ISQED 2003: 377- |
72 | EE | Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David Blaauw: An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. ISVLSI 2003: 149-154 |
71 | EE | Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David Blaauw, Todd M. Austin, Krisztián Flautner, Trevor N. Mudge: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation. MICRO 2003: 7-18 |
70 | EE | Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan: Leakage Current: Moore's Law Meets Static Power. IEEE Computer 36(12): 68-75 (2003) |
69 | EE | Rajendran Panda, Savithri Sundareswaran, David Blaauw: Impact of Low-Impedance Substrate on Power Supply Integrity. IEEE Design & Test of Computers 20(3): 16-22 (2003) |
68 | EE | David Blaauw, Supamas Sirichotiyakul, Chanhee Oh: Driver modeling and alignment for worst-case delay noise. IEEE Trans. VLSI Syst. 11(2): 157-166 (2003) |
67 | EE | David Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta: Static electromigration analysis for on-chip signal interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 39-48 (2003) |
66 | EE | Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. on CAD of Integrated Circuits and Systems 22(1): 49-66 (2003) |
65 | EE | Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj: Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 337-345 (2003) |
64 | EE | Li Ding, David T. Blaauw, Pinaki Mazumder: Accurate crosstalk noise modeling for early signal integrity analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 627-634 (2003) |
63 | EE | David T. Blaauw, Luciano Lavagno: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 962-963 (2003) |
62 | EE | Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul: Probabilistic analysis of interconnect coupling noise. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1188-1203 (2003) |
61 | EE | Aseem Agarwal, Vladimir Zolotov, David T. Blaauw: Statistical timing analysis using bounds and selective enumeration. IEEE Trans. on CAD of Integrated Circuits and Systems 22(9): 1243-1260 (2003) |
2002 | ||
60 | EE | Himanshu Kaul, Dennis Sylvester, David Blaauw: Active shields: a new approach to shielding global wires. ACM Great Lakes Symposium on VLSI 2002: 112-117 |
59 | EE | Sarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul: Estimation of the likelihood of capacitive coupling noise. DAC 2002: 653-658 |
58 | EE | Murat R. Becer, Vladimir Zolotov, David Blaauw, Rajendran Panda, Ibrahim N. Hajj: Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE 2002: 456-464 |
57 | EE | Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar: A precorrected-FFT method for simulating on-chip inductance. ICCAD 2002: 221-227 |
56 | EE | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw: Estimation of signal arrival times in the presence of delay noise. ICCAD 2002: 418-422 |
55 | EE | Vladimir Zolotov, David Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy: Noise propagation and failure criteria for VLSI designs. ICCAD 2002: 587-594 |
54 | EE | Li Ding, David Blaauw, Pinaki Mazumder: Efficient crosstalk noise modeling using aggressor and tree reductions. ICCAD 2002: 595-600 |
53 | EE | Steven M. Martin, Krisztián Flautner, Trevor N. Mudge, David Blaauw: Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads. ICCAD 2002: 721-725 |
52 | EE | Krisztián Flautner, Nam Sung Kim, Steven M. Martin, David Blaauw, Trevor N. Mudge: Drowsy Caches: Simple Techniques for Reducing Leakage Power. ISCA 2002: 148-157 |
51 | EE | Li Ding, Pinaki Mazumder, David Blaauw: Crosstalk noise estimation using effective coupling capacitance. ISCAS (5) 2002: 645-648 |
50 | EE | Ashish Srivastava, Robert Bai, David Blaauw, Dennis Sylvester: Modeling and analysis of leakage power considering within-die process variations. ISLPED 2002: 64-67 |
49 | EE | Murat R. Becer, Rajendran Panda, David Blaauw, Ibrahim N. Hajj: Pre-route Noise Estimation in Deep Submicron Integrated Circuits. ISQED 2002: 413-418 |
48 | EE | Vladimir Zolotov, David Blaauw, Rajendran Panda, Chanhee Oh: Noise Injection and Propagation in High Performance Designs. ISQED 2002: 425-430 |
47 | EE | Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh: False-Noise Analysis Using Resolution Method. ISQED 2002: 437- |
46 | EE | Nam Sung Kim, Krisztián Flautner, David Blaauw, Trevor N. Mudge: Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction. MICRO 2002: 219-230 |
45 | EE | Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David Blaauw: Robust SAT-Based Search Algorithm for Leakage Power Reduction. PATMOS 2002: 167-177 |
44 | EE | Murat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda: Early probabilistic noise estimation for capacitively coupled interconnects. SLIP 2002: 77-83 |
43 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 16-21 |
42 | EE | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula: Statistical timing analysis using bounds and selective enumeration. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 29-36 |
41 | EE | Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driving point model for on-chip RLC interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69 |
40 | EE | Bhavana Thudi, David Blaauw: Efficient switching window computation for cross-talk noise. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 84-91 |
39 | EE | Himanshu Kaul, Dennis Sylvester, David Blaauw: Active shielding of RLC global interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 98-104 |
38 | EE | Alexey Glebov, Sergey Gavrilov, David Blaauw, Vladimir Zolotov: False-noise analysis using logic implications. ACM Trans. Design Autom. Electr. Syst. 7(3): 474-498 (2002) |
37 | EE | David Blaauw, Luciano Lavagno: Guest Editors' Introduction: Hot Topics at This Year's Design Automation Conference. IEEE Design & Test of Computers 19(4): 72-73 (2002) |
36 | EE | Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw: Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits. IEEE Trans. VLSI Syst. 10(2): 79-90 (2002) |
35 | EE | Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi: Inductance model and analysis methodology for high-speed on-chip interconnect. IEEE Trans. VLSI Syst. 10(6): 730-745 (2002) |
34 | EE | David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran: Slope propagation in static timing analysis. IEEE Trans. on CAD of Integrated Circuits and Systems 21(10): 1180-1195 (2002) |
33 | EE | Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw: Hierarchical analysis of power distribution networks. IEEE Trans. on CAD of Integrated Circuits and Systems 21(2): 159-168 (2002) |
32 | EE | David Blaauw, Steven M. Martin, Trevor N. Mudge, Krisztián Flautner: Leakage Current Reduction in VLSI Systems. Journal of Circuits, Systems, and Computers 11(6): 621-636 (2002) |
2001 | ||
31 | EE | Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao: Inductance 101: Analysis and Design Issues. DAC 2001: 329-334 |
30 | EE | Supamas Sirichotiyakul, David Blaauw, Chanhee Oh, Rafi Levy, Vladimir Zolotov, Jingyan Zuo: Driver Modeling and Alignment for Worst-Case Delay Noise. DAC 2001: 720-725 |
29 | EE | Alexey Glebov, Sergey Gavrilov, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov: False-Noise Analysis using Logic Implications. ICCAD 2001: 515- |
28 | EE | Rajendran Panda, Savithri Sundareswaran, David Blaauw: On the interaction of power distribution network with substrate. ISLPED 2001: 388-393 |
27 | EE | David Blaauw, Rajendran Panda: On-Chip Inductance Extraction and Modelin. ISQED 2001: 14 |
26 | EE | Murat R. Becer, David Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov, Jingyan Zuo, Rafi Levy, Ibrahim N. Hajj: A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance. ISQED 2001: 158- |
2000 | ||
25 | David Blaauw, Christian C. Enz, Thaddeus Gabara, Enrico Macii: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000 ACM 2000 | |
24 | EE | David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang: On-chip inductance modeling. ACM Great Lakes Symposium on VLSI 2000: 75-80 |
23 | EE | Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David Blaauw: Hierarchical analysis of power distribution networks. DAC 2000: 150-155 |
22 | EE | Rajat Chaudhry, David Blaauw, Rajendran Panda, Tim Edwards: Current signature compression for IR-drop analysis. DAC 2000: 162-167 |
21 | EE | Rafi Levy, David Blaauw, Gabi Braca, Aurobindo Dasgupta, Amir Grinshpon, Chanhee Oh, Boaz Orshav, Supamas Sirichotiyakul, Vladimir Zolotov: ClariNet: a noise analysis tool for deep submicron design. DAC 2000: 233-238 |
20 | EE | David Blaauw, Rajendran Panda, Abhijit Das: Removing user specified false paths from timing graphs. DAC 2000: 270-273 |
19 | EE | Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw: On-chip inductance modeling and analysis. DAC 2000: 63-68 |
18 | David Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda: Slope Propagation in Static Timing Analysis. ICCAD 2000: 338-343 | |
17 | EE | Rajendran Panda, David Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju: Model and analysis for combined package and on-chip power grid simulation. ISLPED 2000: 179-184 |
16 | EE | Rajat Chaudhry, Rajendran Panda, Tim Edwards, David Blaauw: Design and Analysis of Power Distribution Networks with Accurate RLC Models. VLSI Design 2000: 151-155 |
1999 | ||
15 | Farid N. Najm, Jason Cong, David Blaauw: Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999 ACM 1999 | |
14 | EE | Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David Blaauw: Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC 1999: 436-441 |
13 | EE | Savithri Sundareswaran, David Blaauw, Abhijit Dharchoudhury: A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. VLSI Design 1999: 175-180 |
1998 | ||
12 | EE | Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David Blaauw: Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC 1998: 388-391 |
11 | EE | Abhijit Dharchoudhury, Rajendran Panda, David Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden: Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC 1998: 738-743 |
10 | EE | David Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards: Emerging power management tools for processor design. ISLPED 1998: 143-148 |
1997 | ||
9 | EE | Sergey Gavrilov, Alexey Glebov, S. Rusakov, David Blaauw, Larry G. Jones, Gopalakrishnan Vijayan: Fast power loss calculation for digital static CMOS circuits. ED&TC 1997: 411-415 |
8 | EE | Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David Blaauw: Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662 |
7 | Abhijit Dharchoudhury, David Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning: Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD 1997: 143-148 | |
1995 | ||
6 | EE | Alexey Glebov, David Blaauw, Larry G. Jones: Transistor reordering for low power CMOS gates using an SP-BDD representation. ISLPD 1995: 161-166 |
1994 | ||
5 | EE | Larry G. Jones, David Blaauw: A cache-based method for accelerating switch-level simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 211-218 (1994) |
1990 | ||
4 | EE | David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham: Derivation of signal flow for switch-level simulation. EURO-DAC 1990: 301-305 |
3 | David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham: SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD 1990: 66-69 | |
2 | EE | Daniel G. Saab, Robert B. Mueller-Thuns, David Blaauw, Joseph T. Rahmeh, Jacob A. Abraham: Hierarchical multi-level fault simulation of large systems. J. Electronic Testing 1(2): 139-149 (1990) |
1989 | ||
1 | EE | David Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh: Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC 1989: 179-184 |