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Joonhwan Yi

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2006
3EEJunghee Lee, Joonhwan Yi: Cycle error correction in asynchronous clock modeling for cycle-based simulation. ASP-DAC 2006: 460-465
2EEJoonhwan Yi, John P. Hayes: High-level delay test generation for modular circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 576-590 (2006)
2005
1EEJoonhwan Yi, John P. Hayes: The Coupling Model for Function and Delay Faults. J. Electronic Testing 21(6): 631-649 (2005)

Coauthor Index

1John P. Hayes [1] [2]
2Junghee Lee [3]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)