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2006 | ||
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3 | EE | Junghee Lee, Joonhwan Yi: Cycle error correction in asynchronous clock modeling for cycle-based simulation. ASP-DAC 2006: 460-465 |
2 | EE | Joonhwan Yi, John P. Hayes: High-level delay test generation for modular circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 576-590 (2006) |
2005 | ||
1 | EE | Joonhwan Yi, John P. Hayes: The Coupling Model for Function and Delay Faults. J. Electronic Testing 21(6): 631-649 (2005) |
1 | John P. Hayes | [1] [2] |
2 | Junghee Lee | [3] |