2008 |
33 | EE | Nina Yevtushenko,
Tiziano Villa,
Robert K. Brayton,
Alexandre Petrenko,
Alberto L. Sangiovanni-Vincentelli:
Compositionally Progressive Solutions of Synchronous FSM Equations.
Discrete Event Dynamic Systems 18(1): 51-89 (2008) |
32 | EE | Lin Yuan,
Gang Qu,
Tiziano Villa,
Alberto L. Sangiovanni-Vincentelli:
An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(6): 1159-1164 (2008) |
31 | EE | Anna Bernasconi,
Valentina Ciriani,
Rolf Drechsler,
Tiziano Villa:
Logic Minimization and Testability of 2-SPP Networks.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1190-1202 (2008) |
2007 |
30 | EE | Tiziano Villa,
Svetlana Zharikova,
Nina Yevtushenko,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
A new algorithm for the largest compositionally progressive solution of synchronous language equations.
ACM Great Lakes Symposium on VLSI 2007: 441-444 |
29 | EE | Alan Mishchenko,
Robert K. Brayton,
Jie-Hong Roland Jiang,
Tiziano Villa,
Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations
CoRR abs/0710.4743: (2007) |
2006 |
28 | EE | Anna Bernasconi,
Valentina Ciriani,
Rolf Drechsler,
Tiziano Villa:
Efficient minimization of fully testable 2-SPP networks.
DATE 2006: 1300-1305 |
27 | EE | Christopher Umans,
Tiziano Villa,
Alberto L. Sangiovanni-Vincentelli:
Complexity of two-level logic minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1230-1246 (2006) |
2005 |
26 | EE | Lin Yuan,
Gang Qu,
Tiziano Villa,
Alberto L. Sangiovanni-Vincentelli:
FSM re-engineering and its application in low power state encoding.
ASP-DAC 2005: 254-259 |
25 | EE | Alan Mishchenko,
Robert K. Brayton,
Jie-Hong Roland Jiang,
Tiziano Villa,
Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations.
DATE 2005: 418-423 |
2003 |
24 | EE | Nina Yevtushenko,
Tiziano Villa,
Robert K. Brayton,
Alexandre Petrenko,
Alberto L. Sangiovanni-Vincentelli:
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations.
DATE 2003: 11154-11155 |
2002 |
23 | EE | Robert K. Brayton,
M. Gao,
Jie-Hong Roland Jiang,
Yunjian Jiang,
Yinghua Li,
Alan Mishchenko,
Subarnarekha Sinha,
Tiziano Villa:
Optimization of Multi-Valued Multi-Level Networks.
ISMVL 2002: 168- |
22 | | Nina Yevtushenko,
Tiziano Villa,
Robert K. Brayton,
Alexandre Petrenko,
Alberto L. Sangiovanni-Vincentelli:
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations.
IWLS 2002: 45-50 |
2001 |
21 | EE | Nina Yevtushenko,
Tiziano Villa,
Robert K. Brayton,
Alexandre Petrenko,
Alberto L. Sangiovanni-Vincentelli:
Solution of Parallel Language Equations for Logic Synthesis.
ICCAD 2001: 103- |
2000 |
20 | EE | Andrea Balluchi,
Luca Benvenuti,
Maria Domenica Di Benedetto,
Guido M. Miconi,
Ugo Pozzi,
Tiziano Villa,
Howard Wong-Toi,
Alberto L. Sangiovanni-Vincentelli:
Maximal Safe Set Computation for Idle Speed Control of an Automotive Engine.
HSCC 2000: 32-44 |
19 | EE | Evguenii I. Goldberg,
Luca P. Carloni,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Negative thinking in branch-and-bound: the case of unate covering.
IEEE Trans. on CAD of Integrated Circuits and Systems 19(3): 281-294 (2000) |
1999 |
18 | | Luca P. Carloni,
Evguenii I. Goldberg,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems.
VLSI 1999: 346-361 |
1998 |
17 | EE | Wilsin Gosti,
Alberto L. Sangiovanni-Vincentelli,
Tiziano Villa,
Alexander Saldanha:
An Exact Input Encoding Algorithm for BDDs Representing FSMs.
Great Lakes Symposium on VLSI 1998: 294-300 |
16 | | Arlindo L. Oliveira,
Luca P. Carloni,
Tiziano Villa,
Alberto L. Sangiovanni-Vincentelli:
Exact Minimization of Binary Decision Diagrams Using Implicit Techniques.
IEEE Trans. Computers 47(11): 1282-1296 (1998) |
15 | EE | Evguenii I. Goldberg,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Theory and algorithms for face hypercube embedding.
IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 472-488 (1998) |
1997 |
14 | EE | Evguenii I. Goldberg,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
A fast and robust exact algorithm for face embedding.
ICCAD 1997: 296-303 |
13 | EE | Evguenii I. Goldberg,
Luca P. Carloni,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Negative thinking by incremental problem solving: application to unate covering.
ICCAD 1997: 91-98 |
12 | EE | Timothy Kam,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Theory and algorithms for state minimization of nondeterministic FSMs.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1311-1322 (1997) |
11 | EE | Timothy Kam,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Implicit computation of compatible sets for state minimization of ISFSMs.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 657-676 (1997) |
10 | EE | Tiziano Villa,
Timothy Kam,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Explicit and implicit algorithms for binate covering problems.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 677-691 (1997) |
9 | EE | Tiziano Villa,
Alexander Saldanha,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Symbolic two-level minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 692-708 (1997) |
1996 |
8 | | Robert K. Brayton,
Gary D. Hachtel,
Alberto L. Sangiovanni-Vincentelli,
Fabio Somenzi,
Adnan Aziz,
Szu-Tsung Cheng,
Stephen A. Edwards,
Sunil P. Khatri,
Yuji Kukimoto,
Abelardo Pardo,
Shaz Qadeer,
Rajeev K. Ranjan,
Shaker Sarwary,
Thomas R. Shiple,
Gitanjali Swamy,
Tiziano Villa:
VIS: A System for Verification and Synthesis.
CAV 1996: 428-432 |
7 | | Robert K. Brayton,
Gary D. Hachtel,
Alberto L. Sangiovanni-Vincentelli,
Fabio Somenzi,
Adnan Aziz,
Szu-Tsung Cheng,
Stephen A. Edwards,
Sunil P. Khatri,
Yuji Kukimoto,
Abelardo Pardo,
Shaz Qadeer,
Rajeev K. Ranjan,
Shaker Sarwary,
Thomas R. Shiple,
Gitanjali Swamy,
Tiziano Villa:
VIS.
FMCAD 1996: 248-256 |
1995 |
6 | EE | Timothy Kam,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Implicit state minimization of non-deterministic FSMs.
ICCD 1995: 250-257 |
1994 |
5 | EE | Timothy Kam,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
A Fully Implicit Algorithm for Exact State Minimization.
DAC 1994: 684-690 |
4 | EE | Alexander Saldanha,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Satisfaction of input and output encoding constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 589-602 (1994) |
1991 |
3 | EE | Alexander Saldanha,
Tiziano Villa,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
A Framework for Satisfying Input and Output Encoding Constraints.
DAC 1991: 170-175 |
1990 |
2 | EE | Tiziano Villa,
Alberto L. Sangiovanni-Vincentelli:
NOVA: state assignment of finite state machines for optimal two-level logic implementation.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 905-924 (1990) |
1989 |
1 | EE | Tiziano Villa,
Alberto L. Sangiovanni-Vincentelli:
NOVA: State Assignment of Finite State Machines for Optimal Two-level Logic Implementations.
DAC 1989: 327-332 |