| 2008 |
|---|
| 104 | | Marcelo Lubaszewski,
Michel Renovell,
Rajesh K. Gupta:
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008
ACM 2008 |
| 103 | | Bernd Straube,
Milos Drutarovský,
Michel Renovell,
Peter Gramata,
Mária Fischerová:
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008
IEEE Computer Society 2008 |
| 102 | EE | Piet Engelke,
Ilia Polian,
Michel Renovell,
Sandip Kundu,
Bharath Seshadri,
Bernd Becker:
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008) |
| 2007 |
|---|
| 101 | EE | Philippe Cauvet,
Serge Bernard,
Michel Renovell:
System-in-Package, a Combination of Challenges and Solutions.
European Test Symposium 2007: 193-199 |
| 100 | EE | Vincent Kerzerho,
Philippe Cauvet,
Serge Bernard,
Florence Azaïs,
Mariane Comte,
Michel Renovell:
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
European Test Symposium 2007: 211-216 |
| 99 | EE | Tiago R. Balen,
Fernanda Lima Kastensmidt,
Marcelo Lubaszewski,
Michel Renovell:
Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation.
ISVLSI 2007: 192-197 |
| 98 | EE | Tiago R. Balen,
José Vicente Calvano,
Marcelo Lubaszewski,
Michel Renovell:
Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis.
J. Electronic Testing 23(6): 497-512 (2007) |
| 2006 |
|---|
| 97 | EE | Mariane Comte,
Satoshi Ohtake,
Hideo Fujiwara,
Michel Renovell:
Electrical Behavior of GOS Fault affected Domino Logic Cell.
DELTA 2006: 183-189 |
| 96 | EE | Vincent Kerzerho,
Philippe Cauvet,
Serge Bernard,
Florence Azaïs,
Mariane Comte,
Michel Renovell:
"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC.
European Test Symposium 2006: 159-164 |
| 95 | EE | Tiago R. Balen,
José Vicente Calvano,
Marcelo Lubaszewski,
Michel Renovell:
Functional Test of Field Programmable Analog Arrays.
VTS 2006: 326-333 |
| 94 | EE | Vincent Kerzerho,
Philippe Cauvet,
Serge Bernard,
Florence Azaïs,
Mariane Comte,
Michel Renovell:
A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs.
IEEE Design & Test of Computers 23(3): 234-243 (2006) |
| 93 | EE | Piet Engelke,
Ilia Polian,
Michel Renovell,
Bernd Becker:
Simulating Resistive-Bridging and Stuck-At Faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2181-2192 (2006) |
| 92 | EE | Piet Engelke,
Ilia Polian,
Michel Renovell,
Bernd Becker:
Automatic Test Pattern Generation for Resistive Bridging Faults.
J. Electronic Testing 22(1): 61-69 (2006) |
| 91 | EE | Patrick Girard,
Olivier Héron,
Serge Pravossoudovitch,
Michel Renovell:
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.
J. Electronic Testing 22(2): 161-172 (2006) |
| 2005 |
|---|
| 90 | EE | Ilia Polian,
Sandip Kundu,
Jean Marc Gallière,
Piet Engelke,
Michel Renovell,
Bernd Becker:
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies.
VTS 2005: 343-348 |
| 89 | EE | Gustavo Pereira,
Antonio Andrade Jr.,
Tiago R. Balen,
Marcelo Lubaszewski,
Florence Azaïs,
Michel Renovell:
Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays.
VTS 2005: 389-394 |
| 88 | EE | Jean Marc Gallière,
Michel Renovell,
Florence Azaïs,
Yves Bertrand:
Delay Testing Viability of Gate Oxide Short Defects.
J. Comput. Sci. Technol. 20(2): 195-200 (2005) |
| 87 | EE | Patrick Girard,
Olivier Héron,
Serge Pravossoudovitch,
Michel Renovell:
Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs.
J. Electronic Testing 21(1): 43-55 (2005) |
| 86 | EE | Ilia Polian,
Piet Engelke,
Michel Renovell,
Bernd Becker:
Modeling Feedback Bridging Faults with Non-Zero Resistance.
J. Electronic Testing 21(1): 57-69 (2005) |
| 85 | EE | Florence Azaïs,
Marcelo Lubaszewski,
Pascal Nouet,
Michel Renovell:
A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters.
J. Electronic Testing 21(1): 9-16 (2005) |
| 84 | EE | Tiago R. Balen,
Antonio Q. Andrade,
Florence Azaïs,
Marcelo Lubaszewski,
Michel Renovell:
Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks.
J. Electronic Testing 21(2): 135-146 (2005) |
| 83 | EE | Adoración Rueda,
Michel Renovell,
José Luis Huertas:
Guest Editorial.
J. Electronic Testing 21(3): 203 (2005) |
| 82 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Mariane Comte,
Michel Renovell:
Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications.
J. Electronic Testing 21(3): 291-298 (2005) |
| 81 | EE | Antonio Andrade Jr.,
Gustavo Vieira,
Tiago R. Balen,
Marcelo Lubaszewski,
Florence Azaïs,
Michel Renovell:
Built-in self-test of global interconnects of field programmable analog arrays.
Microelectronics Journal 36(12): 1112-1123 (2005) |
| 2004 |
|---|
| 80 | EE | Antonio Zenteno,
Víctor H. Champac,
Michel Renovell,
Florence Azaïs:
Analysis and Attenuation Proposal in Ground Bounce.
Asian Test Symposium 2004: 460-463 |
| 79 | EE | Patrick Girard,
Olivier Héron,
Serge Pravossoudovitch,
Michel Renovell:
High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.
DELTA 2004: 83-88 |
| 78 | EE | Patrick Girard,
Olivier Héron,
Serge Pravossoudovitch,
Michel Renovell:
BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs.
IOLTS 2004: 187-192 |
| 77 | EE | David Hély,
Marie-Lise Flottes,
Frédéric Bancel,
Bruno Rouzeyre,
Nicolas Bérard,
Michel Renovell:
Scan Design and Secure Chip.
IOLTS 2004: 219-226 |
| 76 | EE | Tiago R. Balen,
Antonio Andrade Jr.,
Florence Azaïs,
Michel Renovell,
Marcelo Lubaszewski:
Testing the Configurable Analog Blocks of Field Programmable Analog Arrays.
ITC 2004: 893-902 |
| 75 | EE | Mehdi Baradaran Tahoori,
Edward J. McCluskey,
Michel Renovell,
Philippe Faure:
A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs.
VTS 2004: 154-170 |
| 74 | EE | Piet Engelke,
Ilia Polian,
Michel Renovell,
Bharath Seshadri,
Bernd Becker:
The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults.
VTS 2004: 171-178 |
| 73 | EE | Tiago R. Balen,
Antonio Andrade Jr.,
Florence Azaïs,
Marcelo Lubaszewski,
Michel Renovell:
An Approach to the Built-In Self-Test of Field Programmable Analog Arrays.
VTS 2004: 383-388 |
| 72 | EE | Serge Bernard,
Mariane Comte,
Florence Azaïs,
Yves Bertrand,
Michel Renovell:
Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors.
J. Electronic Testing 20(3): 257-267 (2004) |
| 71 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Mariane Comte,
Michel Renovell:
Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure.
J. Electronic Testing 20(4): 375-387 (2004) |
| 70 | EE | Alex Gonsales,
Marcelo Lubaszewski,
Luigi Carro,
Michel Renovell:
A New FPGA for DSP Applications Integrating BIST Capabilities.
J. Electronic Testing 20(4): 423-431 (2004) |
| 2003 |
|---|
| 69 | EE | Michel Renovell,
Jean Marc Gallière,
Florence Azaïs,
Yves Bertrand:
Delay Testing of MOS Transistor with Gate Oxide Short.
Asian Test Symposium 2003: 168-173 |
| 68 | EE | Patrick Girard,
Olivier Héron,
Serge Pravossoudovitch,
Michel Renovell:
Defect Analysis for Delay-Fault BIST in FPGAs.
IOLTS 2003: 124-128 |
| 67 | EE | Piet Engelke,
Ilia Polian,
Michel Renovell,
Bernd Becker:
Simulating Resistive Bridging and Stuck-At Faults.
ITC 2003: 1051-1059 |
| 66 | EE | Serge Bernard,
Mariane Comte,
Florence Azaïs,
Yves Bertrand,
Michel Renovell:
A New Methodology For ADC Test Flow Optimization.
ITC 2003: 201-209 |
| 65 | EE | Florence Azaïs,
Yves Bertrand,
Michel Renovell,
André Ivanov,
Sassan Tabatabaei:
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs.
IEEE Design & Test of Computers 20(1): 60-67 (2003) |
| 64 | EE | Uros Kac,
Franc Novak,
Florence Azaïs,
Pascal Nouet,
Michel Renovell:
Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test.
IEEE Design & Test of Computers 20(2): 32-39 (2003) |
| 63 | EE | Michel Renovell,
Jean Marc Gallière,
Florence Azaïs,
Yves Bertrand:
Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short.
J. Electronic Testing 19(4): 377-386 (2003) |
| 62 | EE | Serge Bernard,
Florence Azaïs,
Yves Bertrand,
Michel Renovell:
On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST.
J. Electronic Testing 19(4): 469-479 (2003) |
| 61 | EE | Michel Renovell:
Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs.
Journal of Circuits, Systems, and Computers 12(2): 143-158 (2003) |
| 60 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Mariane Comte,
Michel Renovell:
A-to-D converters static error detection from dynamic parameter measurement.
Microelectronics Journal 34(10): 945-953 (2003) |
| 2002 |
|---|
| 59 | | Manfred Glesner,
Peter Zipf,
Michel Renovell:
Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings
Springer 2002 |
| 58 | EE | Michel Renovell,
Penelope Faure,
Paolo Prinetto,
Yervant Zorian:
Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA.
DELTA 2002: 297-301 |
| 57 | EE | Michel Renovell,
Florence Azaïs,
Yves Bertrand:
Improving Defect Detection in Static-Voltage Testing.
IEEE Design & Test of Computers 19(6): 83-89 (2002) |
| 2001 |
|---|
| 56 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Michel Renovell:
Implementation of a linear histogram BIST for ADCs.
DATE 2001: 590-595 |
| 55 | EE | Serge Bernard,
Florence Azaïs,
Yves Bertrand,
Michel Renovell:
Analog BIST Generator for ADC Testing.
DFT 2001: 338-346 |
| 54 | EE | Michel Renovell:
Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects.
ISQED 2001: 359-364 |
| 53 | | Michel Renovell,
Jean Marc Gallière,
Florence Azaïs,
Serge Bernard,
Yves Bertrand:
Boolean and current detection of MOS transistor with gate oxide short.
ITC 2001: 1039-1048 |
| 52 | | Michel Renovell,
Penelope Faure,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
IS-FPGA : a new symmetric FPGA architecture with implicit scan.
ITC 2001: 924-931 |
| 51 | | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Michel Renovell:
On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST.
VLSI-SOC 2001: 425-436 |
| 50 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Xavier Michel,
Michel Renovell:
A Low-Cost Adaptive Ramp Generator for Analog BIST Applications.
VTS 2001: 266-271 |
| 49 | EE | André Ivanov,
Sumbal Rafiq,
Michel Renovell,
Florence Azaïs,
Yves Bertrand:
On the detectability of CMOS floating gate transistor faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 116-128 (2001) |
| 48 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Michel Renovell:
A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs.
J. Electronic Testing 17(2): 139-147 (2001) |
| 47 | EE | Florence Azaïs,
Serge Bernard,
Yves Bertrand,
Michel Renovell:
Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST.
J. Electronic Testing 17(3-4): 255-266 (2001) |
| 46 | EE | Michel Renovell,
Jean Michel Portal,
Penelope Faure,
Joan Figueras,
Yervant Zorian:
A Discussion on Test Pattern Generation for FPGA - Implemented Circuits.
J. Electronic Testing 17(3-4): 283-290 (2001) |
| 45 | EE | Michel Renovell:
Guest Editorial.
J. Electronic Testing 17(5): 371 (2001) |
| 2000 |
|---|
| 44 | EE | Michel Renovell,
Jean Michel Portal,
Penelope Faure,
Joan Figueras,
Yervant Zorian:
TOF: a tool for test pattern generation optimization of an FPGA application oriented test.
Asian Test Symposium 2000: 323-328 |
| 43 | EE | Luigi Carro,
Érika F. Cota,
Marcelo Lubaszewski,
Yves Bertrand,
Florence Azaïs,
Michel Renovell:
TI-BIST: a temperature independent analog BIST for switched-capacitor filters.
Asian Test Symposium 2000: 78-83 |
| 42 | EE | Érika F. Cota,
Michel Renovell,
Florence Azaïs,
Yves Bertrand,
Luigi Carro,
Marcelo Lubaszewski:
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte.
DATE 2000: 226- |
| 41 | EE | Michel Renovell:
A Specific Test Methodology for Symmetric SRAM-Based FPGAs.
FPL 2000: 300-311 |
| 40 | | Michel Renovell,
Yervant Zorian:
Different experiments in test generation for XILINX FPGAs.
ITC 2000: 854-862 |
| 39 | EE | Michel Renovell,
Florence Azaïs,
Serge Bernard,
Yves Bertrand:
Hardware Resource Minimization for Histogram-Based ADC BIST.
VTS 2000: 247-254 |
| 38 | EE | Michel Renovell,
Florence Azaïs,
J-C. Bodin,
Yves Bertrand:
Combining Functional and Structural Approaches for Switched-Current Circuit Testing.
J. Electronic Testing 16(3): 259-267 (2000) |
| 37 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family.
J. Electronic Testing 16(3): 289-299 (2000) |
| 36 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
Testing the Local Interconnect Resources of SRAM-Based FPGA's.
J. Electronic Testing 16(5): 513-520 (2000) |
| 1999 |
|---|
| 35 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
Minimizing the Number of Test Configurations for Different FPGA Families.
Asian Test Symposium 1999: 363-368 |
| 34 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's.
DATE 1999: 618-622 |
| 33 | | Michel Renovell,
André Ivanov,
Yves Bertrand,
Florence Azaïs,
Sumbal Rafiq:
Optimal conditions for Boolean and current detection of floating gate faults.
ITC 1999: 477-486 |
| 32 | EE | Michel Renovell,
Florence Azaïs,
Yves Bertrand:
Detection of Defects Using Fault Model Oriented Test Sequences.
J. Electronic Testing 14(1-2): 13-22 (1999) |
| 31 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
SRAM-Based FPGAs: Testing the Embedded RAM Modules.
J. Electronic Testing 14(1-2): 159-167 (1999) |
| 1998 |
|---|
| 30 | EE | Sumbal Rafiq,
André Ivanov,
Sassan Tabatabaei,
Michel Renovell:
Testing for Floating Gates Defects in CMOS Circuits.
Asian Test Symposium 1998: 228-236 |
| 29 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface.
Asian Test Symposium 1998: 266-271 |
| 28 | EE | Michel Renovell,
Florence Azaïs,
J-C. Bodin,
Yves Bertrand:
BISTing Switched-Current Circuits.
Asian Test Symposium 1998: 372-377 |
| 27 | EE | Florence Azaïs,
André Ivanov,
Michel Renovell,
Yves Bertrand:
A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs.
Asian Test Symposium 1998: 383-387 |
| 26 | EE | Michel Renovell:
Microsystems Testing: A Challenge.
Asian Test Symposium 1998: 512 |
| 25 | EE | Michel Renovell,
Florence Azaïs,
Yves Bertrand:
Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits.
DATE 1998: 815-821 |
| 24 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
RAM-Based FPGA's: A Test Approach for the Configurable Logic.
DATE 1998: 82-88 |
| 23 | EE | Cecilia Metra,
Michel Renovell,
G. Mojoli,
Jean Michel Portal,
Sandro Pastore,
Joan Figueras,
Yervant Zorian,
Davide Salvi,
Giacomo R. Sechi:
Novel Technique for Testing FPGAs.
DATE 1998: 89- |
| 22 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules.
FPL 1998: 139-148 |
| 21 | | Karl-Erwin Großpietsch,
Jacob A. Abraham,
Johannes Maier,
Hans-Dieter Kochs,
Michel Renovell:
From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel).
FTCS 1998: 296-301 |
| 20 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
SRAM-based FPGA's: testing the LUT/RAM modules.
ITC 1998: 1102-1111 |
| 19 | EE | Florence Azaïs,
Michel Renovell,
Yves Bertrand,
J-C. Bodin:
Design-For-Testability for Switched-Current Circuits.
VTS 1998: 370-375 |
| 18 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
Testing the Interconnect of RAM-Based FPGAs.
IEEE Design & Test of Computers 15(1): 45-50 (1998) |
| 1997 |
|---|
| 17 | EE | Michel Renovell,
Jean Michel Portal,
Joan Figueras,
Yervant Zorian:
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA.
Asian Test Symposium 1997: 254- |
| 16 | EE | Michel Renovell,
Florence Azaïs,
Yves Bertrand:
On-chip analog output response compaction.
ED&TC 1997: 568-572 |
| 15 | | Michel Renovell,
Yves Bertrand:
Test Strategy Sensitivity to Defect Parameters.
ITC 1997: 607-616 |
| 14 | EE | Michel Renovell,
Joan Figueras,
Yervant Zorian:
Test of RAM-based FPGA: methodology and application to the interconnect.
VTS 1997: 230-237 |
| 1996 |
|---|
| 13 | | Michel Renovell,
P. Huc,
Yves Bertrand:
The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault.
EDCC 1996: 205-213 |
| 12 | EE | Michel Renovell,
P. Huc,
Yves Bertrand:
Bridging fault coverage improvement by power supply control.
VTS 1996: 338-343 |
| 11 | EE | Michel Renovell,
Florence Azaïs,
Yves Bertrand:
The multi-configuration: A DFT technique for analog circuits.
VTS 1996: 54-59 |
| 1995 |
|---|
| 10 | EE | Michel Renovell,
P. Huc,
Yves Bertrand:
Serial transistor network modeling for bridging fault simulation.
Asian Test Symposium 1995: 100-106 |
| 9 | EE | Michel Renovell,
Florence Azaïs,
Yves Bertrand:
A design-for-test technique for multistage analog circuits.
Asian Test Symposium 1995: 113-119 |
| 8 | EE | S. Lavabre,
Yves Bertrand,
Michel Renovell,
Christian Landrault:
Test configurations to enhance the testability of sequential circuits.
Asian Test Symposium 1995: 160-168 |
| 7 | EE | Michel Renovell,
P. Huc,
Yves Bertrand:
The concept of resistance interval: a new parametric model for realistic resistive bridging fault.
VTS 1995: 184-189 |
| 6 | EE | Joan Figueras,
Michel Renovell:
Current testing in dynamic CMOS circuits.
J. Electronic Testing 6(1): 127-131 (1995) |
| 1994 |
|---|
| 5 | | Michel Renovell,
P. Huc,
Yves Bertrand:
The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds.
EDCC 1994: 165-177 |
| 1993 |
|---|
| 4 | | Michel Renovell,
Joan Figueras:
Current Testing Viability in Dynamic CMOS Circuits.
DFT 1993: 207-214 |
| 3 | | Yves Bertrand,
Frédéric Bancel,
Michel Renovell:
Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits.
ITC 1993: 989-997 |
| 2 | | Yves Bertrand,
Frédéric Bancel,
Michel Renovell:
A DFT Technique to Improve ATPG Efficiency for Sequential Circuits.
VLSI Design 1993: 51-54 |
| 1992 |
|---|
| 1 | EE | Michel Renovell,
Gaston Cambon:
Electrical analysis and modeling of floating-gate fault.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(11): 1450-1458 (1992) |
