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Jaewon Seo

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2007
10EEMihui Kim, Jaewon Seo, Kijoon Chae: Integrated Notification Architecture Based on Overlay Against DDoS Attacks on Convergence Network. SEUS 2007: 466-476
2006
9EEJaewon Seo, Taewhan Kim, Joonwon Lee: Optimal intratask dynamic voltage-scaling technique and its practical extensions. IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 47-57 (2006)
2005
8EEJaewon Seo, Nikil D. Dutt: A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors. ASP-DAC 2005: 836-841
7 Jaewon Seo, Taewhan Kim, Nikil D. Dutt: Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications. ICCAD 2005: 450-455
2004
6EEJaewon Seo, Taewhan Kim, Ki-Seok Chung: Profile-based optimal intra-task voltage scheduling for hard real-time applications. DAC 2004: 87-92
2003
5EEJaewon Seo, Taewhan Kim, Preeti Ranjan Panda: Memory allocation and mapping in high-level synthesis - an integrated approach. IEEE Trans. VLSI Syst. 11(5): 928-938 (2003)
2002
4EEJaewon Seo, Taewhan Kim, Preeti Ranjan Panda: An integrated algorithm for memory allocation and assignment in high-level synthesis. DAC 2002: 608-611
3EEJaewon Seo, Taewhan Kim: Memory exploration utilizing scheduling effects in high-level synthesis. ISCAS (4) 2002: 73-76
1999
2 Kyungwan Nam, Jaewon Seo, Sunggu Lee, Jong Kim: Synchronous Load Balancing in Hypercube Multicomputers with Faulty Nodes. J. Parallel Distrib. Comput. 58(1): 26-43 (1999)
1997
1EEJaewon Seo, Sunggu Lee, Jong Kim: Synchronous Load Balancing in Hypercube Multicomputers with Faulty Nodes. ICPADS 1997: 414-421

Coauthor Index

1Kijoon Chae (Ki-Joon Chae) [10]
2Ki-Seok Chung [6]
3Nikil D. Dutt (Nikil Dutt) [7] [8]
4Jong Kim [1] [2]
5Mihui Kim [10]
6Taewhan Kim [3] [4] [5] [6] [7] [9]
7Joonwon Lee [9]
8Sunggu Lee [1] [2]
9Kyungwan Nam [2]
10Preeti Ranjan Panda [4] [5]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)