2007 |
10 | EE | Mihui Kim,
Jaewon Seo,
Kijoon Chae:
Integrated Notification Architecture Based on Overlay Against DDoS Attacks on Convergence Network.
SEUS 2007: 466-476 |
2006 |
9 | EE | Jaewon Seo,
Taewhan Kim,
Joonwon Lee:
Optimal intratask dynamic voltage-scaling technique and its practical extensions.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 47-57 (2006) |
2005 |
8 | EE | Jaewon Seo,
Nikil D. Dutt:
A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processors.
ASP-DAC 2005: 836-841 |
7 | | Jaewon Seo,
Taewhan Kim,
Nikil D. Dutt:
Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applications.
ICCAD 2005: 450-455 |
2004 |
6 | EE | Jaewon Seo,
Taewhan Kim,
Ki-Seok Chung:
Profile-based optimal intra-task voltage scheduling for hard real-time applications.
DAC 2004: 87-92 |
2003 |
5 | EE | Jaewon Seo,
Taewhan Kim,
Preeti Ranjan Panda:
Memory allocation and mapping in high-level synthesis - an integrated approach.
IEEE Trans. VLSI Syst. 11(5): 928-938 (2003) |
2002 |
4 | EE | Jaewon Seo,
Taewhan Kim,
Preeti Ranjan Panda:
An integrated algorithm for memory allocation and assignment in high-level synthesis.
DAC 2002: 608-611 |
3 | EE | Jaewon Seo,
Taewhan Kim:
Memory exploration utilizing scheduling effects in high-level synthesis.
ISCAS (4) 2002: 73-76 |
1999 |
2 | | Kyungwan Nam,
Jaewon Seo,
Sunggu Lee,
Jong Kim:
Synchronous Load Balancing in Hypercube Multicomputers with Faulty Nodes.
J. Parallel Distrib. Comput. 58(1): 26-43 (1999) |
1997 |
1 | EE | Jaewon Seo,
Sunggu Lee,
Jong Kim:
Synchronous Load Balancing in Hypercube Multicomputers with Faulty Nodes.
ICPADS 1997: 414-421 |