Ralph H. J. M. Otten

2006
23	EE	Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah: Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2376-2392 (2006)
2004
22	EE	Giuseppe S. Garcea, N. P. van der Meijs, Kees-Jan van der Kolk, Ralph H. J. M. Otten: Statistically Aware Buffer Planning. DATE 2004: 1402-1403
2003
21	EE	Jochen A. G. Jess, K. Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah: Statistical timing for parametric yield prediction of digital integrated circuits. DAC 2003: 932-937
20	EE	Jurjen Westra, Dirk-Jan Jongeneel, Ralph H. J. M. Otten, Chandu Visweswariah: Time Budgeting in a Wireplanning Context. DATE 2003: 10436-10441
19	EE	Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. J. M. Otten: Simultaneous Analytic Area and Power Optimization for Repeater Insertion. ICCAD 2003: 568-573
2002
18	EE	Ralph H. J. M. Otten, Raul Camposano, Patrick Groeneveld: Design Automation for Deepsubmicron: Present and Future. DATE 2002: 650-659
17	EE	Ralph H. J. M. Otten: Shifts in INTEGRATION: 20 years of VLSI design. Integration 32(1-2): 1-4 (2002)
2001
16	EE	Ralph H. J. M. Otten, Giuseppe S. Garcea: Are wires plannable? SLIP 2001: 59-66
2000
15	EE	Raul Camposano, Olivier Coudert, Patrick Groeneveld, Leon Stok, Ralph H. J. M. Otten: Timing closure: the solution and its problems. ASP-DAC 2000: 359-364
14	EE	Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten: Area and search space control for technology mapping. DAC 2000: 86-91
13		Ralph H. J. M. Otten, Paul Stravers: Challenges in Physical Chip Design. ICCAD 2000: 84-91
12	EE	Ralph H. J. M. Otten: What is a floorplan?. ISPD 2000: 201-206
11	EE	Ralph H. J. M. Otten, Robert K. Brayton: Performance planning. Integration 29(1): 1-24 (2000)
10	EE	Dirk-Jan Jongeneel, Ralph H. J. M. Otten: Technology mapping for area and speed. Integration 29(1): 45-66 (2000)
1999
9	EE	Sunil P. Khatri, Amit Mehrotra, Robert K. Brayton, Ralph H. J. M. Otten, Alberto L. Sangiovanni-Vincentelli: A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. DAC 1999: 491-496
1998
8	EE	Ralph H. J. M. Otten, Robert K. Brayton: Planning for Performance. DAC 1998: 122-127
7	EE	Bogdan G. Arsintescu, Ralph H. J. M. Otten: Constraints Space Management for the Layout of Analog IC's. DATE 1998: 971-972
6	EE	Ralph H. J. M. Otten: Global wires: harmful?. ISPD 1998: 104-109
1997
5		Serban Bruma, Ralph H. J. M. Otten: Novel Simulation of Deep-Submicron MOSFET Circuits. ICCD 1997: 62-67
1996
4	EE	Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy: Embedded tutorial: Speed - new paradigms in design for performance. ICCAD 1996: 700
1995
3	EE	Ireneusz Karkowski, Ralph H. J. M. Otten: Retiming Synchronous Circuitry with Imprecise Delays. DAC 1995: 322-326
1990
2	EE	Lukas P. P. P. van Ginneken, Ralph H. J. M. Otten: Optimal slicing of plane point placements. EURO-DAC 1990: 322-326
1989
1	EE	Hong Cai, Ralph H. J. M. Otten: Conflict-free channel definition in building-block layout. IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 981-988 (1989)

Coauthor Index

1	Bogdan G. Arsintescu	[7]
2	Robert K. Brayton	[8] [9] [11] [14]
3	Serban Bruma	[5]
4	Hong Cai	[1]
5	Raul Camposano	[15] [18]
6	Olivier Coudert	[15]
7	Giuseppe S. Garcea	[16] [19] [22]
8	Lukas P. P. P. van Ginneken	[2] [4]
9	Patrick Groeneveld	[15] [18]
10	Jochen A. G. Jess	[21] [23]
11	Dirk-Jan Jongeneel	[10] [14] [20]
12	K. Kalafala	[21] [23]
13	Ireneusz Karkowski	[3]
14	Sunil P. Khatri	[9]
15	Kees-Jan van der Kolk	[22]
16	Amit Mehrotra	[9]
17	N. P. van der Meijs	[19] [22]
18	Srinath R. Naidu	[21] [23]
19	Alberto L. Sangiovanni-Vincentelli	[9]
20	Narendra V. Shenoy	[4]
21	Leon Stok	[15]
22	Paul Stravers	[13]
23	Chandramouli Visweswariah	[21] [23]
24	Chandu Visweswariah	[20]
25	Yosinori Watanabe	[14]
26	Jurjen Westra	[20]

Colors in the list of coauthors