| 2006 |
|---|
| 10 | EE | Yukiko Kubo,
Atsushi Takahashi:
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 725-733 (2006) |
| 2005 |
|---|
| 9 | EE | Yukiko Kubo,
Atsushi Takahashi:
A global routing method for 2-layer ball grid array packages.
ISPD 2005: 36-43 |
| 8 | EE | Yukiko Kubo,
Atsushi Takahashi:
A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages.
IEICE Transactions 88-A(5): 1283-1289 (2005) |
| 7 | EE | Yukiko Kubo,
Hiroshi Miyashita,
Yoji Kajitani,
Kazuyuki Tateishi:
Equidistance routing in high-speed VLSI layout design.
Integration 38(3): 439-449 (2005) |
| 2004 |
|---|
| 6 | EE | Yukiko Kubo,
Hiroshi Miyashita,
Yoji Kajitani,
Kazuyuki Tateishi:
Equidistance routing in high-speed VLSI layout design.
ACM Great Lakes Symposium on VLSI 2004: 220-223 |
| 2002 |
|---|
| 5 | EE | Yukiko Kubo,
Shigetoshi Nakatake,
Yoji Kajitani,
Masahiro Kawakita:
Chip size estimation based on wiring area.
APCCAS (2) 2002: 113-118 |
| 4 | EE | Yukiko Kubo,
Shigetoshi Nakatake,
Yoji Kajitani,
Masahiro Kawakita:
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts.
VLSI Design 2002: 467-472 |
| 3 | EE | Shigetoshi Nakatake,
Yukiko Kubo,
Yoji Kajitani:
Consistent floorplanning with hierarchical superconstraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 42-49 (2002) |
| 2001 |
|---|
| 2 | EE | Shigetoshi Nakatake,
Yukiko Kubo,
Yoji Kajitani:
Consistent floorplanning with super hierarchical constraints.
ISPD 2001: 144-149 |
| 2000 |
|---|
| 1 | EE | Yukiko Kubo,
Yasuhiro Takashima,
Shigetoshi Nakatake,
Yoji Kajitani:
Self-reforming routing for stochastic search in VLSI interconnection layout.
ASP-DAC 2000: 87-92 |
