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Yukiko Kubo

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2006
10EEYukiko Kubo, Atsushi Takahashi: Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 725-733 (2006)
2005
9EEYukiko Kubo, Atsushi Takahashi: A global routing method for 2-layer ball grid array packages. ISPD 2005: 36-43
8EEYukiko Kubo, Atsushi Takahashi: A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages. IEICE Transactions 88-A(5): 1283-1289 (2005)
7EEYukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi: Equidistance routing in high-speed VLSI layout design. Integration 38(3): 439-449 (2005)
2004
6EEYukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi: Equidistance routing in high-speed VLSI layout design. ACM Great Lakes Symposium on VLSI 2004: 220-223
2002
5EEYukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita: Chip size estimation based on wiring area. APCCAS (2) 2002: 113-118
4EEYukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita: Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. VLSI Design 2002: 467-472
3EEShigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani: Consistent floorplanning with hierarchical superconstraints. IEEE Trans. on CAD of Integrated Circuits and Systems 21(1): 42-49 (2002)
2001
2EEShigetoshi Nakatake, Yukiko Kubo, Yoji Kajitani: Consistent floorplanning with super hierarchical constraints. ISPD 2001: 144-149
2000
1EEYukiko Kubo, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani: Self-reforming routing for stochastic search in VLSI interconnection layout. ASP-DAC 2000: 87-92

Coauthor Index

1Yoji Kajitani [1] [2] [3] [4] [5] [6] [7]
2Masahiro Kawakita [4] [5]
3Hiroshi Miyashita [6] [7]
4Shigetoshi Nakatake [1] [2] [3] [4] [5]
5Atsushi Takahashi [8] [9] [10]
6Yasuhiro Takashima [1]
7Kazuyuki Tateishi [6] [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)