| 2008 |
|---|
| 96 | EE | Janar Thoguluva,
Anand Raghunathan,
Srimat T. Chakradhar:
Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor.
DATE 2008: 1148-1153 |
| 95 | EE | Hans Peter Graf,
Srihari Cadambi,
Igor Durdanovic,
Venkata Jakkula,
Murugan Sankaradass,
Eric Cosatto,
Srimat T. Chakradhar:
A Massively Parallel Digital Learning Processor.
NIPS 2008: 529-536 |
| 2007 |
|---|
| 94 | EE | Seongmoon Wang,
Wenlong Wei,
Srimat T. Chakradhar:
Unknown blocking scheme for low control data volume and high observability.
DATE 2007: 33-38 |
| 93 | EE | Mango Chia-Tso Chao,
Kwang-Ting Cheng,
Seongmoon Wang,
Srimat T. Chakradhar,
Wenlong Wei:
A hybrid scheme for compacting test responses with unknown values.
ICCAD 2007: 513-519 |
| 92 | EE | Rajamani Sethuram,
Seongmoon Wang,
Srimat T. Chakradhar,
Michael L. Bushnell:
Zero Cost Test Point Insertion Technique for Structured ASICs.
VLSI Design 2007: 357-363 |
| 91 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Murugan Sankaradass,
Niraj K. Jha,
Srimat T. Chakradhar:
Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.
IEEE Trans. VLSI Syst. 15(6): 699-710 (2007) |
| 2006 |
|---|
| 90 | EE | Mango Chia-Tso Chao,
Kwang-Ting Cheng,
Seongmoon Wang,
Srimat T. Chakradhar,
Wenlong Wei:
Unknown-tolerance analysis and test-quality control for test response compaction using space compactors.
DAC 2006: 1083-1088 |
| 89 | EE | Divya Arora,
Anand Raghunathan,
Srivaths Ravi,
Murugan Sankaradass,
Niraj K. Jha,
Srimat T. Chakradhar:
Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.
DAC 2006: 496-501 |
| 88 | EE | Seongmoon Wang,
Kedarnath J. Balakrishnan,
Srimat T. Chakradhar:
Efficient unknown blocking using LFSR reseeding.
DATE 2006: 1051-1052 |
| 87 | EE | Mango Chia-Tso Chao,
Seongmoon Wang,
Srimat T. Chakradhar,
Wenlong Wei,
Kwang-Ting Cheng:
Coverage loss by using space compactors in presence of unknown values.
DATE 2006: 1053-1054 |
| 86 | EE | Jahangir Hasan,
Srihari Cadambi,
Venkata Jakkula,
Srimat T. Chakradhar:
Chisel: A Storage-efficient, Collision-free Hash-based Network Processing Architecture.
ISCA 2006: 203-215 |
| 85 | EE | Haris Lekatsas,
Jörg Henkel,
Venkata Jakkula,
Srimat T. Chakradhar:
Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems.
VLSI Design 2006: 639-644 |
| 84 | EE | Kedarnath J. Balakrishnan,
Seongmoon Wang,
Srimat T. Chakradhar:
PIDISC: Pattern Independent Design Independent Seed Compression Technique.
VLSI Design 2006: 811-817 |
| 83 | EE | Jiang Xu,
Wayne Wolf,
Jörg Henkel,
Srimat T. Chakradhar:
A design methodology for application-specific networks-on-chip.
ACM Trans. Embedded Comput. Syst. 5(2): 263-280 (2006) |
| 82 | EE | Loganathan Lingappan,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha,
Srimat T. Chakradhar:
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2193-2206 (2006) |
| 81 | EE | Seongmoon Wang,
Srimat T. Chakradhar:
A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1555-1564 (2006) |
| 2005 |
|---|
| 80 | EE | Joel Coburn,
Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
SECA: security-enhanced communication architecture.
CASES 2005: 78-89 |
| 79 | EE | Lei Yang,
Robert P. Dick,
Haris Lekatsas,
Srimat T. Chakradhar:
CRAMES: compressed RAM for embedded systems.
CODES+ISSS 2005: 93-98 |
| 78 | | Mango Chia-Tso Chao,
Seongmoon Wang,
Srimat T. Chakradhar,
Kwang-Ting Cheng:
Response shaper: a novel technique to enhance unknown tolerance for output response compaction.
ICCAD 2005: 80-87 |
| 77 | EE | Mango Chia-Tso Chao,
Seongmoon Wang,
Srimat T. Chakradhar,
Kwang-Ting Cheng:
ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown Values.
ICCD 2005: 147-152 |
| 76 | EE | Jiang Xu,
Wayne Wolf,
Jörg Henkel,
Srimat T. Chakradhar:
H.264 HDTV Decoder Using Application-Specific Networks-On-Chip.
ICME 2005: 1508-1511 |
| 75 | EE | Jiang Xu,
Wayne Wolf,
Jörg Henkel,
Srimat T. Chakradhar:
A methodology for design, modeling, and analysis of networks-on-chip.
ISCAS (2) 2005: 1778-1781 |
| 74 | EE | Haris Lekatsas,
Jörg Henkel,
Venkata Jakkula,
Srimat T. Chakradhar:
A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems.
VLSI Design 2005: 117-123 |
| 73 | EE | Wei Li,
Seongmoon Wang,
Srimat T. Chakradhar,
Sudhakar M. Reddy:
Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage.
VLSI Design 2005: 471-478 |
| 72 | EE | Nikhil Bansal,
Kanishka Lahiri,
Anand Raghunathan,
Srimat T. Chakradhar:
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models.
VLSI Design 2005: 579-585 |
| 71 | EE | Loganathan Lingappan,
Srivaths Ravi,
Anand Raghunathan,
Niraj K. Jha,
Srimat T. Chakradhar:
Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip.
VLSI Design 2005: 65-70 |
| 70 | EE | Tiehan Lv,
Jiang Xu,
Wayne Wolf,
Burak Ozer,
Jörg Henkel,
Srimat T. Chakradhar:
A Methodology for Architectural Design of Multimedia Multiprocessor SoCs.
IEEE Design & Test of Computers 22(1): 18-26 (2005) |
| 2004 |
|---|
| 69 | EE | Seongmoon Wang,
Srimat T. Chakradhar,
Kedarnath J. Balakrishnan:
Re-configurable embedded core test protocol.
ASP-DAC 2004: 234-237 |
| 68 | EE | Srimat T. Chakradhar:
Open architecture test system: not why but when!
ASP-DAC 2004: 337-340 |
| 67 | EE | Seongmoon Wang,
Xiao Liu,
Srimat T. Chakradhar:
Hybrid Delay Scan: A Low Hardware Overhead Scan-Based Delay Test Technique for High Fault Coverage and Compact Test Sets.
DATE 2004: 1296-1301 |
| 66 | EE | Jiang Xu,
Wayne Wolf,
Jörg Henkel,
Srimat T. Chakradhar,
Tiehan Lv:
A Case Study in Networks-on-Chip Design for Embedded Video.
DATE 2004: 770-777 |
| 65 | EE | Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
Tamper Resistance Mechanisms for Secure, Embedded Systems.
VLSI Design 2004: 605- |
| 64 | EE | Jörg Henkel,
Wayne Wolf,
Srimat T. Chakradhar:
On-chip networks: A scalable, communication-centric embedded system design paradigm.
VLSI Design 2004: 845- |
| 63 | EE | Haris Lekatsas,
Jörg Henkel,
Srimat T. Chakradhar,
Venkata Jakkula:
Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems.
IEEE Design & Test of Computers 21(5): 406-415 (2004) |
| 2003 |
|---|
| 62 | EE | Haris Lekatsas,
Jörg Henkel,
Srimat T. Chakradhar,
Venkata Jakkula,
Murugan Sankaradass:
CoCo: a hardware/software platform for rapid prototyping of code compression technologies.
DAC 2003: 306-311 |
| 61 | EE | Seongmoon Wang,
Srimat T. Chakradhar:
A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs.
ITC 2003: 574-583 |
| 60 | EE | Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
Embedding Security in Wireless Embedded Systems.
VLSI Design 2003: 269-270 |
| 59 | EE | Srivaths Ravi,
Anand Raghunathan,
Srimat T. Chakradhar:
Efficient RTL Power Estimation for Large Designs.
VLSI Design 2003: 431-439 |
| 2001 |
|---|
| 58 | EE | Nachiketh R. Potlapally,
Michael S. Hsiao,
Anand Raghunathan,
Ganesh Lakshminarayana,
Srimat T. Chakradhar:
Accurate Power Macro-modeling Techniques for Complex RTL Circuits.
VLSI Design 2001: 235-241 |
| 2000 |
|---|
| 57 | EE | Surendra Bommu,
Srimat T. Chakradhar,
Kiran B. Doreswamy:
Resource-Constrained Compaction of Sequential Circuit Test Sets.
VLSI Design 2000: 398-405 |
| 56 | EE | Michael S. Hsiao,
Srimat T. Chakradhar:
Test Set Compaction Using Relaxed Subsequence Removal.
J. Electronic Testing 16(4): 319-327 (2000) |
| 55 | EE | Michael S. Hsiao,
Srimat T. Chakradhar:
Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits.
J. Electronic Testing 16(4): 329-338 (2000) |
| 54 | EE | Surendra Bommu,
Kiran B. Doreswamy,
Srimat T. Chakradhar:
A Practical Vector Restoration Technique for Large Sequential Circuits.
J. Electronic Testing 16(5): 521-539 (2000) |
| 53 | EE | Angela Krstic,
Srimat T. Chakradhar,
Kwang-Ting Cheng:
Testable Path Delay Fault Cover for Sequential Circuits.
J. Inf. Sci. Eng. 16(5): 673-686 (2000) |
| 1999 |
|---|
| 52 | EE | Angela Krstic,
Kwang-Ting (Tim) Cheng,
Srimat T. Chakradhar:
Testing High Speed VLSI Devices Using Slower Testers.
VTS 1999: 16-21 |
| 51 | EE | Srimat T. Chakradhar,
Sujit Dey:
Resynthesis and retiming for optimum partial scan.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(5): 621-630 (1999) |
| 50 | EE | Angela Krstic,
Kwang-Ting Cheng,
Srimat T. Chakradhar:
Primitive delay faults: identification, testing, and design for testability.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(6): 669-684 (1999) |
| 1998 |
|---|
| 49 | EE | Michael S. Hsiao,
Srimat T. Chakradhar:
Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits.
Asian Test Symposium 1998: 452-457 |
| 48 | EE | Surendra Bommu,
Srimat T. Chakradhar,
Kiran B. Doreswamy:
Vector Restoration Using Accelerated Validation and Refinement.
Asian Test Symposium 1998: 458-466 |
| 47 | EE | Michael S. Hsiao,
Srimat T. Chakradhar:
State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits.
DATE 1998: 577-582 |
| 46 | EE | Surendra Bommu,
Srimat T. Chakradhar,
Kiran B. Doreswamy:
Static compaction using overlapped restoration and segment pruning.
ICCAD 1998: 140-146 |
| 45 | EE | Surendra Bommu,
Srimat T. Chakradhar,
Kiran B. Doreswamy:
Static test sequence compaction based on segment reordering and accelerated vector restoration.
ITC 1998: 954- |
| 44 | EE | Arun Balakrishnan,
Srimat T. Chakradhar:
Peripheral Partitioning and Tree Decomposition for Partial Scan.
VLSI Design 1998: 181-186 |
| 1997 |
|---|
| 43 | | Angela Krstic,
Kwang-Ting Cheng,
Srimat T. Chakradhar:
Design for Primitive Delay Fault Testability.
ITC 1997: 436-445 |
| 42 | EE | Srimat T. Chakradhar,
Vijay Gangaram,
Steven G. Rothweiler:
Deriving Signal Constraints to Accelerate Sequential Test Generation.
VLSI Design 1997: 488-494 |
| 41 | EE | Srimat T. Chakradhar,
Anand Raghunathan:
Bottleneck removal algorithm for dynamic compaction in sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1157-1172 (1997) |
| 40 | EE | Srimat T. Chakradhar,
Steven G. Rothweiler,
Vishwani D. Agrawal:
Redundancy removal and test generation for circuits with non-Boolean primitives.
IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1370-1377 (1997) |
| 1996 |
|---|
| 39 | | Angela Krstic,
Kwang-Ting Cheng,
Srimat T. Chakradhar:
Identification and Test Generation for Primitive Faults.
ITC 1996: 423-432 |
| 38 | EE | Arun Balakrishnan,
Srimat T. Chakradhar:
Sequential Circuits with combinational Test Generation Complexity.
VLSI Design 1996: 111-117 |
| 37 | EE | Anand Raghunathan,
Srimat T. Chakradhar:
Dynamic test Sequence compaction for Sequential Circuits.
VLSI Design 1996: 170-173 |
| 36 | EE | Savita Banerjee,
Srimat T. Chakradhar,
Rabindra K. Roy:
Synchronous Test Generation Model for Asynchronous Circuits.
VLSI Design 1996: 178-185 |
| 35 | EE | Arun Balakrishnan,
Srimat T. Chakradhar:
Retiming with logic duplication transformation: theory and an application to partial scan.
VLSI Design 1996: 296-302 |
| 34 | EE | Srimat T. Chakradhar,
Savita Banerjee,
Rabindra K. Roy,
Dhiraj K. Pradhan:
Synthesis of initializable asynchronous circuits.
IEEE Trans. VLSI Syst. 4(2): 254-263 (1996) |
| 33 | EE | Savita Banerjee,
Rabindra K. Roy,
Srimat T. Chakradhar:
Initialization issues in asynchronous circuit synthesis.
J. Electronic Testing 9(3): 237-250 (1996) |
| 1995 |
|---|
| 32 | EE | Arun Balakrishnan,
Srimat T. Chakradhar:
Software transformations for sequential test generation.
Asian Test Symposium 1995: 266- |
| 31 | EE | Srimat T. Chakradhar,
Anand Raghunathan:
Bottleneck removal algorithm for dynamic compaction and test cycles reduction.
EURO-DAC 1995: 98-104 |
| 30 | EE | Anand Raghunathan,
Srimat T. Chakradhar:
Acceleration techniques for dynamic vector compaction.
ICCAD 1995: 310-317 |
| 29 | EE | Srimat T. Chakradhar:
Optimum retiming of large sequential circuits.
VLSI Design 1995: 135-140 |
| 28 | EE | Arun Balakrishnan,
Srimat T. Chakradhar:
Partial scan design for technology mapped circuits.
VLSI Design 1995: 283-287 |
| 27 | EE | Srimat T. Chakradhar,
Steven G. Rothweiler:
Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives.
VTS 1995: 12-19 |
| 26 | EE | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
A partition and resynthesis approach to testable design of large circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1268-1276 (1995) |
| 25 | EE | Srimat T. Chakradhar,
Mahesh A. Iyer,
Vishwani D. Agrawal:
Energy models for delay testing.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 728-739 (1995) |
| 24 | EE | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
Test function embedding algorithms with application to interconnected finite state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1115-1127 (1995) |
| 23 | EE | Vishwani D. Agrawal,
Srimat T. Chakradhar:
Combinational ATPG theorems for identifying untestable faults in sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1155-1160 (1995) |
| 22 | EE | Sujit Dey,
Srimat T. Chakradhar:
Design of testable sequential circuits by repositioning flip-flops.
J. Electronic Testing 7(1-2): 105-114 (1995) |
| 21 | EE | Srimat T. Chakradhar,
Arun Balakrishnan,
Vishwani D. Agrawal:
An exact algorithm for selecting partial scan flip-flops.
J. Electronic Testing 7(1-2): 83-93 (1995) |
| 1994 |
|---|
| 20 | EE | Srimat T. Chakradhar,
Arun Balakrishnan,
Vishwani D. Agrawal:
An Exact Algorithm for Selecting Partial Scan Flip-Flops.
DAC 1994: 81-86 |
| 19 | EE | Srimat T. Chakradhar,
Sujit Dey:
Resynthesis and Retiming for Optimum Partial Scan.
DAC 1994: 87-93 |
| 18 | | Savita Banerjee,
Rabindra K. Roy,
Srimat T. Chakradhar,
Dhiraj K. Pradhan:
Signal Transition Graph Transformations for Initializability.
EDAC-ETC-EUROASIC 1994: 670 |
| 17 | | Savita Banerjee,
Rabindra K. Roy,
Srimat T. Chakradhar,
Dhiraj K. Pradhan:
Initialization Isuues in the Synthesis of Asynchronous Circuits.
ICCD 1994: 447-452 |
| 16 | | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
A Test Function Architecture for Interconnected Finite State Machines.
VLSI Design 1994: 113-116 |
| 15 | | Srimat T. Chakradhar,
Savita Banerjee,
Rabindra K. Roy,
Dhiraj K. Pradhan:
Synthesis of Initializable Asynchronous Circuits.
VLSI Design 1994: 383-388 |
| 14 | EE | Srimat T. Chakradhar,
Vishwani D. Agrawal,
Michael L. Bushnell:
Energy minimization and design for testability.
J. Electronic Testing 5(1): 57-66 (1994) |
| 1993 |
|---|
| 13 | EE | Srimat T. Chakradhar,
Sujit Dey,
Miodrag Potkonjak,
Steven G. Rothweiler:
Sequential Circuit Delay optimization Using Global Path Delays.
DAC 1993: 483-489 |
| 12 | | Suman Kanjilal,
Srimat T. Chakradhar,
Vishwani D. Agrawal:
A Synthesis Approach to Design for Testability.
ITC 1993: 754-763 |
| 11 | EE | Srimat T. Chakradhar,
Vishwani D. Agrawal,
Steven G. Rothweiler:
A transitive closure algorithm for test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1015-1028 (1993) |
| 10 | EE | Srimat T. Chakradhar,
Suman Kanjilal,
Vishwani D. Agrawal:
Finite state machine synthesis with fault tolerant test function.
J. Electronic Testing 4(1): 57-69 (1993) |
| 1992 |
|---|
| 9 | EE | Srimat T. Chakradhar,
Suman Kanjilal,
Vishwani D. Agrawal:
Finite State Machine Synthesis with Fault Tolerant Test Function.
DAC 1992: 562-567 |
| 8 | EE | Srimat T. Chakradhar,
Michael L. Bushnell:
A solvable class of quadratic 0-1 programming.
Discrete Applied Mathematics 36(3): 233-251 (1992) |
| 7 | EE | Vishwani D. Agrawal,
Srimat T. Chakradhar:
Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems.
IEEE Trans. Parallel Distrib. Syst. 3(6): 739-746 (1992) |
| 1991 |
|---|
| 6 | EE | Srimat T. Chakradhar,
Vishwani D. Agrawal:
A Transitive Closure Based Algorithm for Test Generation.
DAC 1991: 353-358 |
| 1990 |
|---|
| 5 | EE | Srimat T. Chakradhar,
Vishwani D. Agrawal,
Michael L. Bushnell:
Automatic Test Generation Using Quadratic 0-1 Programming.
DAC 1990: 654-659 |
| 4 | | Vishwani D. Agrawal,
Srimat T. Chakradhar:
Logic Simulation and Parallel Processing.
ICCAD 1990: 496-499 |
| 3 | EE | Vishwani D. Agrawal,
Srimat T. Chakradhar:
Performance estimation in a massively parallel system.
SC 1990: 306-313 |
| 2 | EE | Srimat T. Chakradhar,
Vishwani D. Agrawal,
Michael L. Bushnell,
Thomas K. Truong:
Neural Net and Boolean Satisfiability Models of Logic Circuits.
IEEE Design & Test of Computers 7(5): 54-57 (1990) |
| 1 | EE | Srimat T. Chakradhar,
Michael L. Bushnell,
Vishwani D. Agrawal:
Toward massively parallel automatic test generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 981-994 (1990) |
