| |
| 2006 | ||
|---|---|---|
| 3 | EE | Milos Hrkic, John Lillis, Giancarlo Beraudo: An Approach to Placement-Coupled Logic Replication. IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2539-2551 (2006) |
| 2004 | ||
| 2 | EE | Milos Hrkic, John Lillis, Giancarlo Beraudo: An approach to placement-coupled logic replication. DAC 2004: 711-716 |
| 2003 | ||
| 1 | EE | Giancarlo Beraudo, John Lillis: Timing optimization of FPGA placements by logic replication. DAC 2003: 196-201 |
| 1 | Milos Hrkic | [2] [3] |
| 2 | John Lillis | [1] [2] [3] |